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ef706b77c4
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1035 Commits

Author SHA1 Message Date
Evan Cheng
ef706b77c4 Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions. 
llvm-svn: 28029
 2006-05-01 08:54:57 +00:00
Chris Lattner
6ce6942d21 Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c 
with some changes I have to the new CFE.

llvm-svn: 28022
 2006-04-28 23:33:20 +00:00
Evan Cheng
9f21c2daf4 Remove the temporary option: -no-isel-fold-inflight 
llvm-svn: 28012
 2006-04-28 18:54:11 +00:00
Evan Cheng
f843942504 TargetLowering::LowerArguments should return a VBIT_CONVERT of 
FORMAL_ARGUMENTS SDOperand in the return result vector.

llvm-svn: 28009
 2006-04-28 05:25:15 +00:00
Evan Cheng
ff5a88b62e Added a temporary option -no-isel-fold-inflight to control whether a "inflight" 
node can be folded.

llvm-svn: 28003
 2006-04-28 02:09:19 +00:00
Evan Cheng
a6081bc674 Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses 
(VAND, VADD, etc.). Legalizer will assert otherwise.

llvm-svn: 27991
 2006-04-27 08:29:42 +00:00
Chris Lattner
3b27c1bd33 Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and 
PR748.

llvm-svn: 27987
 2006-04-27 05:01:07 +00:00
Evan Cheng
b54140b0d6 Don't forget return void. 
llvm-svn: 27974
 2006-04-25 23:03:35 +00:00
Nate Begeman
7bb910dbe7 Fix the updating of the machine CFG when a PHI node was in a successor of 
the jump table's range check block.  This re-enables 100% dense jump tables
by default on PPC & x86

llvm-svn: 27952
 2006-04-23 06:26:20 +00:00
Nate Begeman
6cfb33a42c Turn of jump tables for a bit, there are still some issues to work out with 
updating the machine CFG.

llvm-svn: 27949
 2006-04-22 23:51:56 +00:00
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Chris Lattner
8f7c394f3a The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap 
miscompares).  Switch RISC targets to use the list-td scheduler, which isn't.

llvm-svn: 27933
 2006-04-21 17:16:16 +00:00
Chris Lattner
3b9a7570cb Fix a couple more memory issues 
llvm-svn: 27930
 2006-04-21 15:32:26 +00:00
Chris Lattner
2ae3ed5e1a Fix a really subtle and obnoxious memory bug that caused issues with an 
llvm-gcc4 boostrap.  Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).

llvm-svn: 27922
 2006-04-20 23:55:59 +00:00
Evan Cheng
618314ed2f Turn a VAND into a VECTOR_SHUFFLE is applicable. 
DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.

llvm-svn: 27874
 2006-04-20 08:56:16 +00:00
Chris Lattner
fa2e364d9c Implement folding of a bunch of binops with undef 
llvm-svn: 27863
 2006-04-20 05:39:12 +00:00
Chris Lattner
a1cf724536 Simplify some code 
llvm-svn: 27846
 2006-04-19 23:17:50 +00:00
Chris Lattner
8c8f1e35c9 Fix handling of calls in functions that use vectors. This fixes a crash on 
the code in GCC PR26546.

llvm-svn: 27780
 2006-04-17 22:10:08 +00:00
Chris Lattner
9bcfa7f378 Codegen insertelement with constant insertion points as scalar_to_vector 
and a shuffle.  For this:

void %test2(<4 x float>* %F, float %f) {
        %tmp = load <4 x float>* %F             ; <<4 x float>> [#uses=2]
        %tmp3 = add <4 x float> %tmp, %tmp              ; <<4 x float>> [#uses=1]
        %tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2               ; <<4 x float>> [#uses=2]
        %tmp6 = add <4 x float> %tmp2, %tmp2            ; <<4 x float>> [#uses=1]
        store <4 x float> %tmp6, <4 x float>* %F
        ret void
}

we now get this on X86 (which will get better):

_test2:
        movl 4(%esp), %eax
        movaps (%eax), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, %xmm1
        shufps $3, %xmm1, %xmm1
        movaps %xmm0, %xmm2
        shufps $1, %xmm2, %xmm2
        unpcklps %xmm1, %xmm2
        movss 8(%esp), %xmm1
        unpcklps %xmm1, %xmm0
        unpcklps %xmm2, %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%eax)
        ret

instead of:

_test2:
        subl $28, %esp
        movl 32(%esp), %eax
        movaps (%eax), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%esp)
        movss 36(%esp), %xmm0
        movss %xmm0, 8(%esp)
        movaps (%esp), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%eax)
        addl $28, %esp
        ret

llvm-svn: 27765
 2006-04-17 19:21:01 +00:00
Chris Lattner
c2f3923b63 Add support for promoting stores from one legal type to another, allowing us 
to write one pattern for vector stores instead of 4.

llvm-svn: 27730
 2006-04-16 01:36:45 +00:00
Chris Lattner
918dbf7203 Make these predicates return true for bit_convert(buildvector)'s as well as 
buildvectors.

llvm-svn: 27723
 2006-04-15 23:38:00 +00:00
Chris Lattner
8882bef982 Make this assertion better 
llvm-svn: 27695
 2006-04-14 06:08:35 +00:00
Evan Cheng
1477d2d08f Promote vector AND, OR, and XOR 
llvm-svn: 27632
 2006-04-12 21:20:24 +00:00
Evan Cheng
ce4e1c0068 Vector type promotion for ISD::LOAD and ISD::SELECT 
llvm-svn: 27606
 2006-04-12 16:33:18 +00:00
Chris Lattner
70d68fcfcb Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload 
llvm-svn: 27604
 2006-04-12 16:20:43 +00:00
Chris Lattner
3df4b4ca55 Don't memoize vloads in the load map! Don't memoize them anywhere here, let 
getNode do it.  This fixes CodeGen/Generic/2006-04-11-vecload.ll

llvm-svn: 27602
 2006-04-12 03:25:41 +00:00
Evan Cheng
be9f313cd8 Only get Tmp2 for cases where number of operands is > 1. Fixed return void. 
llvm-svn: 27586
 2006-04-11 06:33:39 +00:00
Chris Lattner
651f0655d0 add some todos 
llvm-svn: 27580
 2006-04-11 02:00:08 +00:00
Chris Lattner
d02e72ffc3 Add basic support for legalizing returns of vectors 
llvm-svn: 27578
 2006-04-11 01:31:51 +00:00
Evan Cheng
d333e6853c Missing break 
llvm-svn: 27559
 2006-04-10 18:54:36 +00:00
Chris Lattner
2c57f7285e Add code generator support for VSELECT 
llvm-svn: 27542
 2006-04-08 22:22:57 +00:00
Chris Lattner
9e4a289fae Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns 
to match again :)

llvm-svn: 27533
 2006-04-08 05:34:25 +00:00
Chris Lattner
fc546e1780 Codegen shufflevector as VVECTOR_SHUFFLE 
llvm-svn: 27529
 2006-04-08 04:15:24 +00:00
Chris Lattner
12c1bd4cbc add a sanity check: LegalizeOp should return a value that is the same type 
as its input.

llvm-svn: 27528
 2006-04-08 04:13:17 +00:00
Evan Cheng
375bec1961 INSERT_VECTOR_ELT lowering bug: 
store vector to $esp
  store element to $esp + sizeof(VT) * index
  load  vector from $esp
The bug is VT is the type of the vector element, not the type of the vector!

llvm-svn: 27517
 2006-04-08 01:46:37 +00:00
Chris Lattner
234481e1ba Stub out shufflevector 
llvm-svn: 27514
 2006-04-08 01:19:25 +00:00
Evan Cheng
e5eefd369a 1. If both vector operands of a vector_shuffle are undef, turn it into an undef. 
2. A shuffle mask element can also be an undef.

llvm-svn: 27472
 2006-04-06 23:20:43 +00:00
Chris Lattner
fe2926cf46 Make a vector live across blocks have the correct Vec type. This fixes 
CodeGen/X86/2006-04-04-CrossBlockCrash.ll

llvm-svn: 27436
 2006-04-05 06:54:42 +00:00
Evan Cheng
abd8dc54c2 Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expanded 
or custom lowering fails.

llvm-svn: 27432
 2006-04-05 06:07:11 +00:00
Chris Lattner
cad2bfa3d7 Do not create ZEXTLOAD's unless we are before legalize or the operation is 
legal.

llvm-svn: 27402
 2006-04-04 17:39:18 +00:00
Chris Lattner
136a27d0d0 * Add supprot for SCALAR_TO_VECTOR operations where the input needs to be 
promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
  to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.

llvm-svn: 27399
 2006-04-04 17:23:26 +00:00
Chris Lattner
85dc06c29e Constant fold bitconvert(undef) 
llvm-svn: 27391
 2006-04-04 01:02:22 +00:00
Chris Lattner
d13dd8ef5c Add a missing check, this fixes UnitTests/Vector/sumarray.c 
llvm-svn: 27375
 2006-04-03 17:29:28 +00:00
Chris Lattner
d9902c3de0 Add a missing check, which broke a bunch of vector tests. 
llvm-svn: 27374
 2006-04-03 17:21:50 +00:00
Andrew Lenharth
b133e47444 back this out 
llvm-svn: 27367
 2006-04-03 03:16:50 +00:00
Andrew Lenharth
91c6f28ad6 This should be a win of every arch 
llvm-svn: 27364
 2006-04-02 21:42:45 +00:00
Chris Lattner
dbdc830c83 Add a little dag combine to compile this: 
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
        %tmp1 = load <4 x float>* %in           ; <<4 x float>> [#uses=1]
        %tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 )           ; <int> [#uses=1]
        %tmp = seteq int %tmp, 0                ; <bool> [#uses=1]
        %tmp3 = cast bool %tmp to int           ; <int> [#uses=1]
        ret int %tmp3
}

into this:

_AreSecondAndThirdElementsBothNegative:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256, r4
        li r4, lo16(LCPI1_0)
        lis r5, ha16(LCPI1_0)
        lvx v0, 0, r3
        lvx v1, r5, r4
        vcmpgefp. v0, v1, v0
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        mtspr 256, r2
        blr

instead of this:

_AreSecondAndThirdElementsBothNegative:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256, r4
        li r4, lo16(LCPI1_0)
        lis r5, ha16(LCPI1_0)
        lvx v0, 0, r3
        lvx v1, r5, r4
        vcmpgefp. v0, v1, v0
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        xori r3, r3, 1
        cntlzw r3, r3
        srwi r3, r3, 5
        mtspr 256, r2
        blr

llvm-svn: 27356
 2006-04-02 06:11:11 +00:00
Chris Lattner
c76f9e8691 Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work with PowerPC. 
llvm-svn: 27349
 2006-04-02 05:06:04 +00:00
Chris Lattner
f15063eadf Implement the Expand action for binary vector operations to break the binop 
into elements and operate on each piece.  This allows generic vector integer
multiplies to work on PPC, though the generated code is horrible.

llvm-svn: 27347
 2006-04-02 03:57:31 +00:00
Chris Lattner
389e309bfb Intrinsics that just load from memory can be treated like loads: they don't 
have to serialize against each other.  This allows us to schedule lvx's
across each other, for example.

llvm-svn: 27346
 2006-04-02 03:41:14 +00:00