Evan Cheng
ef8a1bcbc3
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
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llvm-svn: 37895
2007-07-05 07:13:32 +00:00
Dan Gohman
9cbc3fb1ab
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Owen Anderson
89558a0db6
Fix the build.
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llvm-svn: 37705
2007-06-22 16:59:54 +00:00
Evan Cheng
c49382e48f
Allow predicated immediate ARM to ARM calls.
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llvm-svn: 37659
2007-06-19 21:05:09 +00:00
Dan Gohman
b60d8a92c9
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Evan Cheng
7b433a2954
Mark these instructions clobbersPred. They modify the condition code register.
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llvm-svn: 37468
2007-06-06 10:17:05 +00:00
Evan Cheng
8a52b80cdf
Opcode modifier s comes after condition code. e.g. addlts, not addslt.
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llvm-svn: 37388
2007-06-01 20:51:29 +00:00
Evan Cheng
c2fec89f4a
Make jumptable non-predicable for now.
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llvm-svn: 37381
2007-06-01 00:56:15 +00:00
Evan Cheng
5df14b3451
For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
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llvm-svn: 37349
2007-05-29 23:32:06 +00:00
Dale Johannesen
f01566b705
Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
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llvm-svn: 37271
2007-05-21 22:42:04 +00:00
Dale Johannesen
8f484d16b0
Add some patterns for PIC PC-relative loads and stores.
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llvm-svn: 37269
2007-05-21 22:14:33 +00:00
Evan Cheng
e875732104
Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
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llvm-svn: 37199
2007-05-18 01:53:54 +00:00
Evan Cheng
d3f1a259db
Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
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llvm-svn: 37118
2007-05-16 20:50:01 +00:00
Evan Cheng
6943cefdcd
Conditional branch is not a barrier.
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llvm-svn: 37103
2007-05-16 07:45:54 +00:00
Evan Cheng
9f0ffdf4b3
Add PredicateOperand to all ARM instructions that have the condition field.
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llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Evan Cheng
73abcaa525
Switch BCC, MOVCCr, etc. to PredicateOperand.
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llvm-svn: 36948
2007-05-08 21:08:43 +00:00
Dale Johannesen
0a4acbf6ac
change per review
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llvm-svn: 36519
2007-04-28 00:36:37 +00:00
Dale Johannesen
74feb7979a
Prevent Thumb code from generating ARM instructions
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llvm-svn: 36518
2007-04-27 22:17:18 +00:00
Lauro Ramos Venancio
f385b56870
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
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llvm-svn: 36506
2007-04-27 13:54:47 +00:00
Chris Lattner
87296c2580
dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll
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llvm-svn: 36222
2007-04-17 22:39:58 +00:00
Lauro Ramos Venancio
7e21418680
- Divides the comparisons in two types: comparisons that only use N and Z
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flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
Lauro Ramos Venancio
8b2e32de5a
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
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llvm-svn: 35381
2007-03-27 16:19:21 +00:00
Lauro Ramos Venancio
11d7d3fcaf
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
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mov lr, pc
bx lr
So, the function was not called.
llvm-svn: 35218
2007-03-20 17:57:23 +00:00
Evan Cheng
4fec9d7228
Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool.
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llvm-svn: 35207
2007-03-20 08:11:30 +00:00
Evan Cheng
8d374caead
Fix naming inconsistencies.
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llvm-svn: 35163
2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582
Special LDR instructions to load from non-pc-relative constantpools. These are
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rematerializable. Only used for constant generation for now.
llvm-svn: 35162
2007-03-19 07:20:03 +00:00
Evan Cheng
389cf8e719
Constant generation instructions are re-materializable.
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llvm-svn: 35161
2007-03-19 07:09:02 +00:00
Evan Cheng
bf4ca3b491
ARM callseq_end should have a input flag operand so it would be scheduled right after the call.
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llvm-svn: 33832
2007-02-03 09:11:58 +00:00
Evan Cheng
0f07707270
- Fix codegen for pc relative constant (e.g. JT) in thumb mode:
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.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
llvm-svn: 33664
2007-01-30 20:37:08 +00:00
Jim Laskey
23ed7d2625
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
Evan Cheng
5d0be572b5
Code clean up. Use def : pat instead of defining new instructions.
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llvm-svn: 33368
2007-01-19 20:27:35 +00:00
Evan Cheng
c6e1d453d3
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
Rafael Espindola
d1baea3471
implement missing compares
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patch by Lauro
bug fixed by me
llvm-svn: 32795
2006-12-31 18:52:39 +00:00
Lauro Ramos Venancio
7bfe536783
Implement SELECT_CC (f32/f64) for ARM.
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llvm-svn: 32762
2006-12-28 13:11:14 +00:00
Rafael Espindola
da5b9584ce
remove duplicated line
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bug noticed by Lauro
llvm-svn: 32761
2006-12-28 12:51:40 +00:00
Lauro Ramos Venancio
2cde823f98
This patch defines extloadi1 and fixes an internal compiler error on
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arm.
llvm-svn: 32760
2006-12-26 19:30:42 +00:00
Rafael Espindola
7c4245c4e3
more general matching of the MVN instruction
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llvm-svn: 32484
2006-12-12 17:10:13 +00:00
Rafael Espindola
d29cb12dfc
use MVN to handle small negative constants
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llvm-svn: 32459
2006-12-12 01:03:11 +00:00
Rafael Espindola
b8163fd828
add mvn
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llvm-svn: 32454
2006-12-12 00:37:38 +00:00
Rafael Espindola
514fcabb29
fix truncstorei1
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llvm-svn: 32364
2006-12-08 18:41:21 +00:00
Rafael Espindola
5daebfdae0
implement load effective address similar to the alpha backend
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remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
Rafael Espindola
f7b898d497
initial implementation of addressing mode 2
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TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
Chris Lattner
7c265ad682
remove dead/redundant vars
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llvm-svn: 31435
2006-11-03 23:48:56 +00:00
Rafael Espindola
a52f709418
implement zextload bool and truncstore bool
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llvm-svn: 31348
2006-11-01 14:13:27 +00:00
Chris Lattner
71dc932fcb
implement uncond branch insertion, mark branches with isBranch.
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llvm-svn: 31160
2006-10-24 16:47:57 +00:00
Rafael Espindola
70f01d5cc0
implement STRB and STRH
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llvm-svn: 31138
2006-10-23 20:34:27 +00:00
Rafael Espindola
c08546401b
use Pat to implement extloadi8 and extloadi16
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llvm-svn: 31052
2006-10-19 17:05:03 +00:00
Rafael Espindola
35e92188e0
implement undef
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llvm-svn: 31049
2006-10-19 13:45:00 +00:00
Rafael Espindola
722266845b
implement extloadi8 and extloadi16
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llvm-svn: 31047
2006-10-19 12:45:04 +00:00