NAKAMURA Takumi
ef9dd6b5db
test/CodeGen/X86/vec_cast.ll: [PR8311] Add explicit -mtriple=x86_64-linux and -mtriple=x86_64-win32. Thanks to Nadav, it might be fixed in r126424.
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llvm-svn: 127060
2011-03-05 02:38:02 +00:00
Bruno Cardoso Lopes
52c64a2eb3
Improve div/rem node handling on mips. Patch by Akira Hatanaka
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llvm-svn: 127034
2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes
1deaf83a77
Add testcase for r127032
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llvm-svn: 127033
2011-03-04 20:48:39 +00:00
Dan Gohman
a8389213a0
When decling to reuse existing expressions that involve casts, ignore
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bitcasts, which are really no-ops here. This fixes slowdowns on
MultiSource/Applications/aha and others.
llvm-svn: 127031
2011-03-04 20:46:46 +00:00
Joerg Sonnenberger
5f2f5fa638
Be nice to Xcore and the XMOS assembler and avoid quoting section names
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that contain only letters, digits and the characters "_" and ".".
llvm-svn: 127028
2011-03-04 20:03:14 +00:00
Bruno Cardoso Lopes
99619e5bef
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
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llvm-svn: 127027
2011-03-04 20:01:52 +00:00
Devang Patel
3efe510847
XFAIL for all. These tests are darwin specific anyway.
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llvm-svn: 127022
2011-03-04 19:38:10 +00:00
Devang Patel
23ee9fdba3
Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global.
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llvm-svn: 127019
2011-03-04 19:11:05 +00:00
Kalle Raiskila
6e33c92ffb
Allow vector shifts (shl,lshr,ashr) on SPU.
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There was a previous implementation with patterns that would
have matched e.g.
shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.
llvm-svn: 126998
2011-03-04 13:19:18 +00:00
Kalle Raiskila
72cfda1a29
Allow load from constant on SPU.
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A 'load <4 x i32>* null' crashes llc before this fix.
llvm-svn: 126995
2011-03-04 12:00:11 +00:00
Eli Friedman
26f5c96de3
Revert r123908; the code in question is completely untested and wrong.
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llvm-svn: 126964
2011-03-03 22:33:23 +00:00
Joerg Sonnenberger
bb93506f95
Bug#9033: For the ELF assembler output, always quote the section name.
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llvm-svn: 126963
2011-03-03 22:31:08 +00:00
Stuart Hastings
efcae37ebf
Test case for r126864. Radar 9056407.
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llvm-svn: 126900
2011-03-02 23:41:40 +00:00
David Greene
2fd6d03bc9
[AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement
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missing patterns for them.
Add a SIMD test subdirectory to hold tests for SIMD instruction
selection correctness and quality.
'
llvm-svn: 126845
2011-03-02 17:23:43 +00:00
Cameron Zwarich
6a4612ba06
Eliminate the unused CodeGenPrepare option to split critical edges.
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llvm-svn: 126825
2011-03-02 03:31:46 +00:00
Che-Liang Chiou
2e7bb6da4c
Extend initial support for primitive types in PTX backend
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- Allow i16, i32, i64, float, and double types, using the native .u16,
.u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.
Patch by Justin Holewinski
llvm-svn: 126824
2011-03-02 03:20:28 +00:00
Dan Gohman
0823ebc79b
Don't re-use existing addrec expansions if they contain casts.
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This fixes PR9259.
llvm-svn: 126812
2011-03-02 01:34:10 +00:00
Evan Cheng
5275ba7f98
Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648.
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llvm-svn: 126811
2011-03-02 01:08:17 +00:00
Bill Wendling
304dda7810
Narrow right shifts need to encode their immediates differently from a normal
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shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
2011-03-01 01:00:59 +00:00
Jakob Stoklund Olesen
2bec7738eb
Fix typo introduced by r126661: "Fix a typo which ..."
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llvm-svn: 126666
2011-02-28 19:18:59 +00:00
Evan Cheng
4e6d375744
Fix a typo which cause dag combine crash. rdar://9059537.
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llvm-svn: 126661
2011-02-28 18:45:27 +00:00
Duncan Sands
0f78cf8a37
Windows codegen also dies on this, so restrict to the platform it was
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actually tested on.
llvm-svn: 126652
2011-02-28 14:22:08 +00:00
Duncan Sands
195d2036d0
Make this test x86 specific because the ARM backend can't handle it.
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llvm-svn: 126650
2011-02-28 12:30:47 +00:00
Che-Liang Chiou
4026d01040
Add preliminary support for .f32 in the PTX backend.
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- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
to accept the float type.
- Add appropriate test cases.
Patch by Justin Holewinski
llvm-svn: 126636
2011-02-28 06:34:09 +00:00
Duncan Sands
b6f7dcb996
Legalize support for fpextend of vector. PR9309.
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llvm-svn: 126574
2011-02-27 14:41:27 +00:00
NAKAMURA Takumi
b35d45a714
Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs.
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It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).
llvm-svn: 126568
2011-02-27 08:47:19 +00:00
Cameron Zwarich
764320383d
Fix PR9324 / <rdar://problem/9052489> by handling the case where a PHI has no uses.
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llvm-svn: 126567
2011-02-27 08:06:01 +00:00
Cameron Zwarich
1409977fe2
Give a test file a more sensible name so that it can hold more test cases.
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llvm-svn: 126566
2011-02-27 08:05:57 +00:00
Benjamin Kramer
412ffed4f0
Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic.
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1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible
It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.
llvm-svn: 126557
2011-02-26 22:48:07 +00:00
Bob Wilson
6bbffe19e9
Add patterns to use post-increment addressing for Neon VST1-lane instructions.
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llvm-svn: 126477
2011-02-25 06:42:42 +00:00
Nadav Rotem
ab7cf630f4
Enable support for vector sext and trunc:
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Limit the folding of any_ext and sext into the load operation to scalars.
Limit the active-bits trunc optimization to scalars.
Document vector trunc and vector sext in LangRef.
Similar to commit 126080 (for enabling zext).
llvm-svn: 126424
2011-02-24 21:01:34 +00:00
Devang Patel
bac565c8a3
Move arch specific tests in arch specific directories.
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llvm-svn: 126401
2011-02-24 19:06:27 +00:00
Richard Osborne
a8df984a31
Add XCore intrinsic for eeu instruction.
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llvm-svn: 126384
2011-02-24 13:39:18 +00:00
Cameron Zwarich
724eb8706a
Merge information about the number of zero, one, and sign bits of live-out
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registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.
llvm-svn: 126380
2011-02-24 10:00:25 +00:00
Evan Cheng
9db7b1367d
Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory
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operands starts at index 2, not 1.
rdar://9045024
PR9305
llvm-svn: 126359
2011-02-24 02:36:52 +00:00
Devang Patel
e8ade74a52
Use DW_FORM_data2 for DW_AT_language and let users use DW_LANG_lo_user=0x8000 to DW_LANG_hi_user=0xffff range.
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llvm-svn: 126339
2011-02-23 22:37:04 +00:00
Devang Patel
dc0160e163
Check only relevant strings in output to increase stability of the tests.
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llvm-svn: 126338
2011-02-23 22:35:57 +00:00
Richard Osborne
d9564589f6
Add XCore intrinsic for clre instruction.
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llvm-svn: 126322
2011-02-23 18:52:05 +00:00
Richard Osborne
4a55817288
Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable
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events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
llvm-svn: 126320
2011-02-23 18:35:59 +00:00
Richard Osborne
aaac1b01fd
Add XCore intrinsic for the setv instruction.
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llvm-svn: 126315
2011-02-23 16:46:37 +00:00
Richard Osborne
aa39bf94b4
Add XCore intrinsic for settw instruction.
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llvm-svn: 126313
2011-02-23 14:45:03 +00:00
Evan Cheng
da40bcab44
More fcopysign correctness and performance fix.
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The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.
The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
vmov.i32 d1, #0x80000000
vbsl d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702
llvm-svn: 126295
2011-02-23 02:24:55 +00:00
NAKAMURA Takumi
c59b707d50
Revert r126195, "test/CodeGen/X86/vec_cast.ll: Mark as XFAIL: migw,win32 for workaround of PR8311."
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It seems it affected configuration --target=i686-pc-mingw32, I don't know and will investigate why.
llvm-svn: 126217
2011-02-22 08:22:54 +00:00
NAKAMURA Takumi
5663670e56
Relax expressions and add explicit triplets -linux and -win32.
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llvm-svn: 126216
2011-02-22 07:21:59 +00:00
NAKAMURA Takumi
d1a4c5b79b
Relax expressions and add explicit triplets -linux and -win32.
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llvm-svn: 126215
2011-02-22 07:21:51 +00:00
NAKAMURA Takumi
606d6d5dc3
Relax expressions and add explicit triplets -linux and -win32.
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llvm-svn: 126214
2011-02-22 07:21:42 +00:00
NAKAMURA Takumi
7a721b6fb6
Relax expressions and add explicit triplets -linux and -win32.
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llvm-svn: 126213
2011-02-22 07:21:33 +00:00
NAKAMURA Takumi
7ea92257f9
Relax expressions and add explicit triplets -linux and -win32.
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llvm-svn: 126212
2011-02-22 07:21:25 +00:00
NAKAMURA Takumi
e601f83a06
Relax expressions and add explicit triplets -linux and -win32.
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On @foobar(double %d, double* %x),
AMD64: (%xmm0, %rdi)
Win64: (%xmm0, %rdx) (not %rcx!)
llvm-svn: 126211
2011-02-22 07:21:17 +00:00
NAKAMURA Takumi
78e74f5921
Relax expressions and add explicit triplets -linux and -win32.
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llvm-svn: 126210
2011-02-22 07:21:08 +00:00