Jim Grosbach
7152d0423b
80-column cleanup of file header comments
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llvm-svn: 86408
2009-11-07 22:00:39 +00:00
Jim Grosbach
e42dc83a9f
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
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llvm-svn: 85406
2009-10-28 17:33:28 +00:00
Evan Cheng
b740190d2e
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
Evan Cheng
d555fec28c
Refactor. Get rid of a few more getOpcode() calls.
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llvm-svn: 77164
2009-07-26 18:55:14 +00:00
David Goodwin
85bcdffa4f
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
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llvm-svn: 76919
2009-07-24 00:16:18 +00:00
Evan Cheng
7a6b20df7f
Let callers decide the sub-register index on the def operand of rematerialized instructions.
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Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
llvm-svn: 75900
2009-07-16 09:20:10 +00:00
David Goodwin
49fbd8d6b7
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
David Goodwin
94209a4c31
Generalize opcode selection in ARMBaseRegisterInfo.
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llvm-svn: 75036
2009-07-08 20:28:28 +00:00
David Goodwin
c571c4b457
Push methods into base class in preparation for sharing.
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llvm-svn: 75020
2009-07-08 18:31:39 +00:00
David Goodwin
81075a5d30
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
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llvm-svn: 74731
2009-07-02 22:18:33 +00:00
