RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-29 23:12:55 +01:00
Code Issues Projects Releases Wiki Activity
19,871 Commits 4 Branches 5 Tags 704 MiB
f32ef9a37f
Commit Graph

64 Commits

Author SHA1 Message Date
Jim Laskey
f32ef9a37f 1. Use SubtargetFeatures in llc/lli. 
2. Propagate feature "string" to all targets.

3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.

llvm-svn: 23192
 2005-09-01 21:38:21 +00:00
Nate Begeman
a978ae8b7d Remove the X86 and PowerPC Simple instruction selectors; their time has 
passed.

llvm-svn: 22886
 2005-08-18 23:53:15 +00:00
Chris Lattner
6e4c443e45 add a beta option for turning on dag->dag isel 
llvm-svn: 22837
 2005-08-17 19:33:30 +00:00
Chris Lattner
543dd2e01c Turn loop strength reduction on by default. 
Only run createLowerConstantExpressionsPass for the simple isel.  The DAG
isel has no need for it.

llvm-svn: 22794
 2005-08-15 23:47:04 +00:00
Nate Begeman
55d6c917c5 Remove support for 64b PPC, it's been broken for a long time. It'll be 
back once a DAG->DAG ISel exists.

llvm-svn: 22778
 2005-08-13 05:59:16 +00:00
Chris Lattner
93820f4ad7 Consolidate the GPOpt stuff to all use the Subtarget, instead of still 
depending on the command line option.  Now the command line option just
sets the subtarget as appropriate.  G5 opts will now default to on on
G5-enabled nightly testers among other machines.

llvm-svn: 22688
 2005-08-05 22:05:03 +00:00
Chris Lattner
852038daec don't crash when running the PPC backend on non-ppc hosts without specifying 
a subtarget.

llvm-svn: 22677
 2005-08-05 16:17:22 +00:00
Nate Begeman
84d0a2806a Use the new subtarget support to automatically choose the correct ABI 
and asm printer for PowerPC if one is not specified.

llvm-svn: 22659
 2005-08-04 20:49:48 +00:00
Nate Begeman
09997f1012 Add Subtarget support to PowerPC. Next up, using it. 
llvm-svn: 22644
 2005-08-04 07:12:09 +00:00
Jeff Cohen
bd51ec7461 Eliminate all remaining tabs and trailing spaces. 
llvm-svn: 22523
 2005-07-27 06:12:32 +00:00
Nate Begeman
7259cc60c4 Support building non-PIC 
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.

llvm-svn: 22494
 2005-07-21 20:44:43 +00:00
Chris Lattner
1766305e60 revert to using 4-byte alignment for doubles, as specified by the ABI 
llvm-svn: 22493
 2005-07-21 19:17:18 +00:00
Nate Begeman
ae843fcefe Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5. 
8-byte align doubles.

llvm-svn: 22486
 2005-07-20 22:42:00 +00:00
Nate Begeman
b83789d611 Integrate SelectFPExpr into SelectExpr. This gets PPC32 closer to being 
automatically generated from a target description.

llvm-svn: 22470
 2005-07-19 16:51:05 +00:00
Chris Lattner
06282f51cf Refactor the addPassesToEmitAssembly interface into a addPassesToEmitFile 
interface.

llvm-svn: 22282
 2005-06-25 02:48:37 +00:00
Misha Brukman
1fef885677 Remove trailing whitespace 
llvm-svn: 21425
 2005-04-21 23:30:14 +00:00
Nate Begeman
ecb5b5c028 Make pattern isel default for ppc 
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default

llvm-svn: 21309
 2005-04-15 22:12:16 +00:00
Nate Begeman
152dbbe856 Remove 64 bit simple ISel, it never worked correctly 
Add initial (buggy) implementation of 64 bit pattern ISel

llvm-svn: 21096
 2005-04-05 08:51:15 +00:00
Nate Begeman
833c1d0994 Implement more of the PPC32 Pattern ISel: 
1) dynamic stack alloc
2) loads
3) shifts
4) subtract
5) immediate form of add, and, or, xor
6) change flag from -pattern-isel to -enable-ppc-pattern-isel

Remove dead arguments from getGlobalBaseReg in the simple ISel

llvm-svn: 20810
 2005-03-24 06:28:42 +00:00
Nate Begeman
0e77845b7e Addition of the PPC32 Pattern ISel. While it is far from complete, it will 
be brought up to parity with the current simple ISel in the coming days.
Currently, -pattern-isel is required to trigger it.

llvm-svn: 20805
 2005-03-24 04:41:43 +00:00
Chris Lattner
b205d87afe cleanup the cfg after lsr 
llvm-svn: 20410
 2005-03-02 21:56:00 +00:00
Chris Lattner
798b18474c Add a temporary option for llc-beta: -enable-lsr-for-ppc, which turns on 
Loop Strength Reduction.

llvm-svn: 20399
 2005-03-02 06:19:22 +00:00
Chris Lattner
6131b06f73 Use the target triple to pick this target. 
llvm-svn: 18830
 2004-12-12 17:40:28 +00:00
Chris Lattner
1de5cd0fd0 The LLVM bool type shall have 1 byte alignment on PPC. 
llvm-svn: 18311
 2004-11-28 21:16:45 +00:00
Chris Lattner
026387ccbc The JIT works enough 
llvm-svn: 18228
 2004-11-25 04:14:54 +00:00
Chris Lattner
9554912215 Remove this method. 
llvm-svn: 18159
 2004-11-23 18:47:42 +00:00
Nate Begeman
f096183b46 Don't return value from void function. This is only temporary anyway while 
the JIT is made to work!

llvm-svn: 18155
 2004-11-23 10:04:49 +00:00
Chris Lattner
30c5ade43e Be really paranoid about not breaking stuff yet 
llvm-svn: 18152
 2004-11-23 06:56:18 +00:00
Chris Lattner
e74f5f8a4e Move JITInfo from PPCTM to PPC32TM 
llvm-svn: 18140
 2004-11-23 05:56:40 +00:00
Chris Lattner
3ff7bafe17 Remove this method, it's not clear how it could be implemented indep of 32 or 64-bit mode 
llvm-svn: 18038
 2004-11-20 04:17:17 +00:00
Chris Lattner
9c356da87d Disable the JIT until it can sorta kinda work. 
llvm-svn: 17230
 2004-10-25 20:53:41 +00:00
Chris Lattner
6ff0fd4837 bling bling! 
llvm-svn: 16873
 2004-10-10 16:26:13 +00:00
Nate Begeman
e816600b3e All PPC instructions are now auto-printed 
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out

llvm-svn: 16163
 2004-09-04 05:00:00 +00:00
Reid Spencer
c4abcbefb1 Changes For Bug 352 
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.

llvm-svn: 16137
 2004-09-01 22:55:40 +00:00
Chris Lattner
cd2b92c36e Do not register ppc64 yet, as it breaks the SparcV9 backend 
llvm-svn: 15955
 2004-08-20 18:09:18 +00:00
Misha Brukman
70f027b623 LR needs to be saved at 16-byte offset on a 64-bit arch 
llvm-svn: 15929
 2004-08-19 21:36:14 +00:00
Misha Brukman
17c41c8bed No need for an `is64bit' flag 
llvm-svn: 15857
 2004-08-17 05:06:47 +00:00
Nate Begeman
224deaa061 Replace PowerPCPEI.cpp with target independant PrologEpilogInserter 
llvm-svn: 15746
 2004-08-14 22:16:36 +00:00
Misha Brukman
f2c87f4794 Disable PPC64 backend by default because LLC cannot choose automatically between 
SparcV9 and PowerPC64 without target triples, since they are both 64-bit
big-endian targets.

llvm-svn: 15688
 2004-08-12 17:16:43 +00:00
Misha Brukman
14bf47d0d9 * Move AIX into the llvm namespace to be accessed from RegisterInfo 
* Mark InstrInfo with 32 vs. 64 bit flag
* Enable the 64-bit isel and asm printer

llvm-svn: 15672
 2004-08-11 23:47:08 +00:00
Misha Brukman
1f4fb14301 Hyphenate ##-bit and remove first-person from comments. 
llvm-svn: 15663
 2004-08-11 13:35:44 +00:00
Nate Begeman
6120e8f04f Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm printer. 
llvm-svn: 15662
 2004-08-11 07:40:04 +00:00
Misha Brukman
694c9ff1a6 Breaking up the PowerPC target into 32- and 64-bit subparts, Part III: the rest. 
llvm-svn: 15636
 2004-08-11 00:11:25 +00:00
Misha Brukman
3da9167cc4 CodePrinter -> AsmPrinter 
llvm-svn: 15599
 2004-08-09 22:27:45 +00:00
Chris Lattner
bbf11b1e1d Changes commited for Nate Begeman: 
Use a PowerPC specific prolog epilog inserter to control where spilled
callee save regs are placed on the stack.
Get rid of implicit return address stack slot, save return address reg
(LR) in appropriate slot
Improve code generated for functions that don't have calls or access
globals


Note from Chris: PowerPCPEI will eventually be eliminated, once the
functionality is merged into CodeGen/PrologEpilogInserter.cpp

llvm-svn: 15536
 2004-08-06 06:58:50 +00:00
Misha Brukman
ef0cbd830c Run the branch selection pass right before the asm printer. 
Patch by Nate Begeman.

llvm-svn: 15285
 2004-07-27 18:39:34 +00:00
Misha Brukman
2ad2adf8cb Bool alignment on MacOSX/PowerPC is 4 bytes. 
llvm-svn: 15122
 2004-07-23 01:11:46 +00:00
Misha Brukman
3e3d141a92 Shorts are aligned to 2 bytes, bools to 1 byte (in structs). 
llvm-svn: 15048
 2004-07-20 20:59:57 +00:00
Misha Brukman
1942534307 Double alignment in structs is 4 bytes, not 8. Patch by Nate Begeman. 
llvm-svn: 15034
 2004-07-20 15:43:25 +00:00
Misha Brukman
c52cf4db44 We don't really need to #include IPO.h into this file. 
llvm-svn: 14911
 2004-07-17 18:37:46 +00:00