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2480 Commits

Author SHA1 Message Date
David Goodwin
048b80a70a Checkpoint more aggressive anti-dependency breaking for post-ra scheduler. 
llvm-svn: 84658
 2009-10-20 19:54:44 +00:00
Dan Gohman
e0ace5c4eb Make TranslateX86CC return COND_INVALID instead of aborting when it 
encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.

llvm-svn: 84640
 2009-10-20 16:22:37 +00:00
Dan Gohman
b1528d73d1 Re-apply r84295, with fixes to how the loop "top" and "bottom" blocks are 
tracked. Instead of trying to manually keep track of these locations
while doing complex modifications, just recompute them when they're needed.
This fixes a bug in which the TopMBB and BotMBB were not correctly updated,
leading to invalid transformations.

llvm-svn: 84598
 2009-10-20 04:50:37 +00:00
Evan Cheng
029a85b791 If the physical register being spilled does not have an interval, spill its sub-registers instead. 
llvm-svn: 84586
 2009-10-20 01:31:09 +00:00
Jim Grosbach
2fb5eb1264 Enable allocation of R3 in Thumb1 
llvm-svn: 84563
 2009-10-19 22:57:03 +00:00
Chris Lattner
b9bbaf7f4d convert to filecheck syntax and make a lot more aggressive. 
llvm-svn: 84517
 2009-10-19 18:27:56 +00:00
Anton Korobeynikov
26ed697cf2 Revert r84295, this unbreaks llvm-gcc bootstrap on x86-64/linux 
llvm-svn: 84516
 2009-10-19 18:21:09 +00:00
Chris Lattner
6fd5bc3ba0 rename test 
llvm-svn: 84515
 2009-10-19 18:18:07 +00:00
Torok Edwin
e6df0e6397 Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS. 
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.

llvm-svn: 84485
 2009-10-19 11:00:58 +00:00
Daniel Dunbar
347b151bc2 Teach lit that the .c files in 'test/CodeGen/CellSPU/useful-harnesses' aren't tests. 
llvm-svn: 84460
 2009-10-19 03:53:55 +00:00
Nate Begeman
1308a36647 Add support for matching shuffle patterns with palignr. 
llvm-svn: 84459
 2009-10-19 02:17:23 +00:00
Evan Cheng
eb82c3743a Turn on post-alloc scheduling for x86. 
llvm-svn: 84431
 2009-10-18 19:57:27 +00:00
Dan Gohman
f5225573b7 Enhance CodePlacementOpt's unconditional intra-loop branch elimination logic 
to be more general and understand more varieties of loops.

Teach CodePlacementOpt to reorganize the basic blocks of a loop so that
they are contiguous. This also includes a fair amount of logic for preserving
fall-through edges while doing so. This fixes a BranchFolding-ism where blocks
which can't be made to use a fall-through edge and don't conveniently fit
anywhere nearby get tossed out to the end of the function.

llvm-svn: 84295
 2009-10-17 00:32:43 +00:00
Mon P Wang
72d9f1ecfe Update tests to use FileCheck 
llvm-svn: 84282
 2009-10-16 22:09:05 +00:00
Mon P Wang
7d294603e7 Add test case for r84279 
llvm-svn: 84280
 2009-10-16 22:07:19 +00:00
Dan Gohman
ef1f246d88 Move zext and sext casts fed by loads into the same block as the 
load, to help SelectionDAG fold them into the loads, unless
conditions are unfavorable.

llvm-svn: 84271
 2009-10-16 20:59:35 +00:00
Evan Cheng
b1580b5c48 Enable post-alloc scheduling for all ARM variants except for Thumb1. 
llvm-svn: 84249
 2009-10-16 06:11:08 +00:00
Sandeep Patel
c0762ba283 Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng. 
llvm-svn: 84212
 2009-10-15 22:25:32 +00:00
Sanjiv Gupta
d279da3360 Re-apply 84180 with the fixed test case. 
llvm-svn: 84195
 2009-10-15 19:26:25 +00:00
Jakob Stoklund Olesen
311774b780 Move Blackfin intrinsics into the Target/Blackfin directory. 
llvm-svn: 84194
 2009-10-15 18:50:52 +00:00
Dan Gohman
27c126770a Make CodePlacementOpt align loops, rather than loop headers. The 
header is just the entry block to the loop, and it needn't be at
the top of the loop in the code layout.

Remove the code that suppressed loop alignment for outer loops,
so that outer loops are aligned.

llvm-svn: 84158
 2009-10-15 00:36:22 +00:00
Evan Cheng
f46b194f84 When LiveVariables is adding implicit-def to model "partial dead", add the earlyclobber marker if the superreg def has it. 
llvm-svn: 84153
 2009-10-14 23:39:27 +00:00
Dan Gohman
1d10570630 Fix this test to account for a movl $0 being emitted as an xor now, 
and convert it to FileCheck.

llvm-svn: 84065
 2009-10-14 00:28:48 +00:00
Bob Wilson
d66a3fd73b Revise ARM inline assembly memory operands to require the memory address to 
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022
 2009-10-13 20:50:28 +00:00
Sandeep Patel
1584038783 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
llvm-svn: 84009
 2009-10-13 18:59:48 +00:00
Dan Gohman
b5a0207b98 Don't forget to mark RAX as live-out of the function when arranging for 
it to hold the address of an sret return value, for x86-64 ABI purposes.

Also, fix the test that was originally intended to test this to actually
test it, using FileCheck.

llvm-svn: 83853
 2009-10-12 16:36:12 +00:00
Benjamin Kramer
34c117d8b7 Eliminate some redundant llvm-as calls. 
llvm-svn: 83837
 2009-10-12 09:31:55 +00:00
Anton Korobeynikov
deadc3ed2d Add missed mem-mem move patterns 
llvm-svn: 83812
 2009-10-11 23:03:53 +00:00
Anton Korobeynikov
986885b62e Add MSP430 mem-mem insts support. Patch by Brian Lucas with some my refinements 
llvm-svn: 83811
 2009-10-11 23:03:28 +00:00
Anton Korobeynikov
fb18fbf80d Add bunch of MSP430 'feature' tests. Patch by Brian Lucas with some my refinements 
llvm-svn: 83809
 2009-10-11 23:02:38 +00:00
Anton Korobeynikov
329def1675 Implement 'm' memory operand properly 
llvm-svn: 83785
 2009-10-11 19:14:21 +00:00
Anton Korobeynikov
1f9ff55cbc It seems that OR operation does not affect status reg at all. 
Remove impdef of SRW. This fixes PR4779

llvm-svn: 83739
 2009-10-10 22:17:47 +00:00
Dan Gohman
b535009219 Update this test; the code is the same but it gets counted as one 
fewer remat.

llvm-svn: 83690
 2009-10-09 23:31:04 +00:00
Dan Gohman
f2ae9c6220 Fix the x86 test-shrink optimization so that it doesn't shrink comparisons 
when one of the bits being tested would end up being the sign bit in the
narrower type, and a signed comparison is being performed, since this would
change the result of the signed comparison. This fixes PR5132.

llvm-svn: 83670
 2009-10-09 20:35:19 +00:00
Bob Wilson
011e458c11 Merge a bunch of NEON tests into larger files so they run faster. 
llvm-svn: 83667
 2009-10-09 20:20:54 +00:00
Bob Wilson
de71518edb Convert some ARM tests with lots of greps to use FileCheck. 
llvm-svn: 83651
 2009-10-09 17:20:46 +00:00
Evan Cheng
439044f330 Fix a logic error that caused non-rematable loop invariants loads to be licm'ed out of loop. 
llvm-svn: 83622
 2009-10-09 06:21:52 +00:00
Bob Wilson
d48cacb92f Commit one last NEON test to use FileCheck. That's all of them now! 
llvm-svn: 83617
 2009-10-09 05:31:56 +00:00
Bob Wilson
a8746e6bd1 Convert more NEON tests to use FileCheck. 
llvm-svn: 83616
 2009-10-09 05:14:48 +00:00
Evan Cheng
b1f6b5fccc Reset kill markers after live interval is reconstructed. 
llvm-svn: 83608
 2009-10-09 01:17:11 +00:00
Bob Wilson
8092fef09a Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
llvm-svn: 83600
 2009-10-09 00:01:36 +00:00
Bob Wilson
979cb24a81 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
llvm-svn: 83598
 2009-10-08 23:51:31 +00:00
Bob Wilson
233992bc56 Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
llvm-svn: 83596
 2009-10-08 23:38:24 +00:00
Bob Wilson
395adfabef Convert more NEON tests to use FileCheck. 
llvm-svn: 83595
 2009-10-08 23:33:03 +00:00
Bob Wilson
5b96a53ffe Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Bob Wilson
1fe8b7e27c Convert more NEON tests to use FileCheck. 
llvm-svn: 83587
 2009-10-08 22:33:53 +00:00
Bob Wilson
7209d78713 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Anton Korobeynikov
f9c811c948 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. 
llvm-svn: 83572
 2009-10-08 20:43:22 +00:00
Bob Wilson
3a55fe2105 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00
Richard Osborne
1719935e3f Add some peepholes for signed comparisons using ashr X, X, 32. 
llvm-svn: 83549
 2009-10-08 15:38:17 +00:00