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f3dc101cd2
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13930 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
f3dc101cd2 Teach X86FloatingPoint that a register can be killed multiple times by the same 
instruction.

This instruction would crash the pass:

  INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>

Now it doesn't.

llvm-svn: 102509
 2010-04-28 18:28:37 +00:00
Evan Cheng
d4fe387eb8 Enable i16 to i32 promotion by default. 
llvm-svn: 102493
 2010-04-28 08:30:49 +00:00
Evan Cheng
4e5846c61e Unbreak the build. Only form shld / shrd after legalization. 
llvm-svn: 102488
 2010-04-28 02:25:18 +00:00
Devang Patel
570e9d53a7 Emit debug info for byval parameters. 
llvm-svn: 102486
 2010-04-28 01:39:28 +00:00
Evan Cheng
b7bb090d5d Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32). 
llvm-svn: 102485
 2010-04-28 01:18:01 +00:00
Chris Lattner
19715b76b7 further simplify EmitAlignment by eliminating the 
ForcedAlignBits argument, tweaking the single client of it.

llvm-svn: 102484
 2010-04-28 01:08:40 +00:00
Stuart Hastings
0768675d1b Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163. 
llvm-svn: 102477
 2010-04-28 00:35:10 +00:00
Devang Patel
00f63442db Use MachineOperand::is* predicates. 
llvm-svn: 102472
 2010-04-27 22:24:37 +00:00
Evan Cheng
65a95091cf Fix obvious typos. 
llvm-svn: 102467
 2010-04-27 21:46:03 +00:00
Evan Cheng
f9531c1175 SRA promotion is also not free. 
llvm-svn: 102456
 2010-04-27 19:48:31 +00:00
Chris Lattner
9292bad5f5 on darwin empty functions need to codegen into something of non-zero length, 
otherwise labels get incorrectly merged.  We handled this by emitting a 
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes.  Handle this by emitting a noop.  This
is more gross than it should be because arm/ppc are not fully mc'ized yet.

This fixes rdar://7908505

llvm-svn: 102400
 2010-04-26 23:37:21 +00:00
Bob Wilson
ece63716aa Handle register-to-register copies within the tGPR class. 
Radar 7896289

llvm-svn: 102396
 2010-04-26 23:20:08 +00:00
Dale Johannesen
90c4aeebbd Handle target-specific form of DBG_VALUE in AsmPrinter. 
llvm-svn: 102373
 2010-04-26 20:07:31 +00:00
Dale Johannesen
c4d2156a7c Add PPC AsmPrinter handling for target-specific form of 
DBG_VALUE, and a cautionary comment.

llvm-svn: 102371
 2010-04-26 20:05:01 +00:00
Evan Cheng
2be8b0e2bf Promoting 16-bit cmp / test aren't free. Don't do it. 
llvm-svn: 102366
 2010-04-26 19:06:11 +00:00
Evan Cheng
cedc094434 Remove a redundant comment. 
llvm-svn: 102326
 2010-04-26 08:16:57 +00:00
Evan Cheng
409147d401 Add PPC specific emitFrameIndexDebugValue. 
llvm-svn: 102325
 2010-04-26 07:39:36 +00:00
Evan Cheng
1c8d01121f Add ARM specific emitFrameIndexDebugValue. 
llvm-svn: 102324
 2010-04-26 07:39:25 +00:00
Evan Cheng
dc0ce1eae8 - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue. 
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.

llvm-svn: 102323
 2010-04-26 07:38:55 +00:00
Dale Johannesen
d27eedab6d Stop abusing EmitInstrWithCustomInserter for target-dependent 
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets.  Add a new hook instead.
No functional change.

llvm-svn: 102320
 2010-04-25 21:33:54 +00:00
Evan Cheng
ec4cc9ce14 Avoid promoting a i16 node if it would eliminate a (store (op (load))) opportunity. 
llvm-svn: 102237
 2010-04-24 04:44:57 +00:00
Dan Gohman
6a48222bd8 Change TargetData's algorithm for computing defualt vector type 
alignment to match what's used in clang and GCC for __alignof, rather
than trying to guess what Legalize is going to be doing.

llvm-svn: 102206
 2010-04-23 19:41:15 +00:00
Stuart Hastings
ad81819149 Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU testcases. Radar 6881029. 
llvm-svn: 102199
 2010-04-23 19:03:32 +00:00
Evan Cheng
9228d598ad Fix X86ISD::CMP i16 to i32 promotion. 
llvm-svn: 102192
 2010-04-23 18:21:16 +00:00
Jim Grosbach
b9dccb6103 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.

llvm-svn: 102144
 2010-04-22 23:24:18 +00:00
Dan Gohman
d819e7fc95 Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel 
and into SelectionDAGBuilder and FastISel.

llvm-svn: 102123
 2010-04-22 20:46:50 +00:00
Evan Cheng
da832d5c85 - It's not safe to promote rotates (at least not trivially). 
- Some code refactoring.

llvm-svn: 102111
 2010-04-22 20:19:46 +00:00
Johnny Chen
c23127cb7e Modified some assert() msg strings; no other functionality change. 
llvm-svn: 102008
 2010-04-21 18:37:48 +00:00
Evan Cheng
dbfb7dc438 Implement -disable-non-leaf-fp-elim which disable frame pointer elimination 
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181

llvm-svn: 101984
 2010-04-21 03:18:23 +00:00
Evan Cheng
0f4671b0dd isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted. 
llvm-svn: 101979
 2010-04-21 01:47:12 +00:00
Evan Cheng
e67a37c4ce Trim include. 
llvm-svn: 101978
 2010-04-21 01:39:06 +00:00
Dan Gohman
4ff2d817a3 Add more const qualifiers on TargetMachine and friends. 
llvm-svn: 101977
 2010-04-21 01:34:56 +00:00
Johnny Chen
6e4b1607ee Thumb instructions which have reglist operands at the end and predicate operands 
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.

llvm-svn: 101974
 2010-04-21 01:01:19 +00:00
Bill Wendling
9bf4b878e0 Handle a displacement location in 64-bit as an RIP-relative displacement. It 
fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work:

target triple = "x86_64-apple-darwin"

define double @func(double %a) {
  %tmp1 = fmul double %a, 5.000000e-01            ; <double> [#uses=1]
  ret double %tmp1
}

define i32 @main() nounwind {
  %1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0]
  ret i32 0
}

llvm-svn: 101965
 2010-04-21 00:34:04 +00:00
Chris Lattner
6db0f451a7 teach the x86 address matching stuff to handle 
(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.

This finishes off PR1135.  Before we compiled the block to:
to:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	leaq	2(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	leaq	1(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	addq	$3, %rdx
	movl	%esi, (%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

Now we produce:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	movl	%esi, 8(%rdi,%rdx,4)
	movl	%esi, 4(%rdi,%rdx,4)
	movl	%esi, 12(%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

llvm-svn: 101958
 2010-04-20 23:18:40 +00:00
Dale Johannesen
510282d54b Because of the EMMS problem, right now we have to support 
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own.  This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)

llvm-svn: 101951
 2010-04-20 22:34:09 +00:00
Johnny Chen
d7ffae797f Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error), 
instead of just asserting.

llvm-svn: 101942
 2010-04-20 21:29:28 +00:00
Johnny Chen
bd5bf58029 For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', 
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915
 2010-04-20 17:28:50 +00:00
Chris Lattner
04fb51984f teach cellspu how to return i8 and i16 from calls, 
patch by Kalle Raiskila!

llvm-svn: 101875
 2010-04-20 05:36:09 +00:00
Chris Lattner
339a3cd59b disable optimizations in this directory for MSVC9. This avoids 
an optimizer infinite loop on the file, PR6866.

llvm-svn: 101854
 2010-04-20 01:11:32 +00:00
Johnny Chen
4f388a02d6 Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands where 
d==15 is considered illegal.  Return false instead of assert().

llvm-svn: 101852
 2010-04-20 01:01:57 +00:00
Eric Christopher
53e7e0fcfb Remove the palignr intrinsics now that we lower them to vector shuffles, 
shifts and null vectors. Autoupgrade these to what we'd lower them to.

Add a testcase to exercise this.

llvm-svn: 101851
 2010-04-20 00:59:54 +00:00
Johnny Chen
1b36569ba8 More IT instruction error-handling improvements from fuzzing. 
llvm-svn: 101839
 2010-04-20 00:15:41 +00:00
Johnny Chen
2d0dca9099 Better error handling of invalid IT mask '0000', instead of just asserting. 
llvm-svn: 101827
 2010-04-19 23:02:58 +00:00
Dan Gohman
45789ce594 Delete an unnecessary reference to SelectionDAGISel::BB. 
llvm-svn: 101824
 2010-04-19 22:48:45 +00:00
Johnny Chen
fe24cdbba8 According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.

llvm-svn: 101817
 2010-04-19 21:19:52 +00:00
Evan Cheng
8efe9e0351 More progress on promoting i16 operations to i32 for x86. Work in progress. 
llvm-svn: 101808
 2010-04-19 19:29:22 +00:00
Johnny Chen
b386de1758 Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand 
instructions should have Rd (Inst{11-8}) != 0b1111.

Ref: A6.3 32-bit Thumb instruction encoding
     A6.3.11 Data-processing (shifted register)
llvm-svn: 101788
 2010-04-19 17:16:40 +00:00
Johnny Chen
091c01cb2f ARM disassembler did not react to recent changes to the NEON instruction table. 
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.

llvm-svn: 101784
 2010-04-19 16:20:34 +00:00
Anton Korobeynikov
dc153b7539 Add missed part of prev. commit 
llvm-svn: 101755
 2010-04-18 20:41:42 +00:00