5 Commits

Author	SHA1	Message	Date
Chandler Carruth	87f14b4eec	Re-sort all of the includes with ./utils/sort_includes.py so that ... subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685	2014-01-07 11:48:04 +00:00
Alp Toker	e845f8af67	Correct word hyphenations ... This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities and contractions in nearby lines. llvm-svn: 196471	2013-12-05 05:44:44 +00:00
Jim Grosbach	067a40bdd0	ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane. ... These instructions, such as vmul.f32, require the second source operand to be in D0-D15 rather than the full D0-D31. When optimizing, make sure to account for that by constraining the register class of a replacement virtual register to be compatible with the virtual register(s) it's replacing. I've been unsuccessful in creating a non-fragile regression test. This issue was detected by the LLVM nightly test suite running on an A15 (Bullet). PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093 llvm-svn: 189972	2013-09-04 19:08:44 +00:00
Craig Topper	9729e843cb	Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. ... llvm-svn: 185540	2013-07-03 15:07:05 +00:00
Silviu Baranga	ff316abe9d	Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc. ... llvm-svn: 177169	2013-03-15 18:28:25 +00:00