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Author SHA1 Message Date
Jim Grosbach
3eb4f0de5e Update comments. These are for assembler, too. 
llvm-svn: 135107
 2011-07-13 23:33:10 +00:00
Owen Anderson
c68f12ff30 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. 
llvm-svn: 135106
 2011-07-13 23:22:26 +00:00
Bill Wendling
e896e46a8c Add code to handle a "frameless" unwind stack. 
The frameless unwind stack has a special encoding, the algorithm for which is in
"permuteEncode".

llvm-svn: 135103
 2011-07-13 23:03:31 +00:00
Jim Grosbach
c0ec4205e2 ARM Assembler support for DBG instruction. 
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
 2011-07-13 22:59:38 +00:00
Bruno Cardoso Lopes
f29783ee55 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases. 
llvm-svn: 135099
 2011-07-13 22:28:55 +00:00
Jim Grosbach
25a4b8922d ARM parsing and encoding tests for CMN/CMP. 
llvm-svn: 135098
 2011-07-13 22:26:58 +00:00
David Greene
a72634bcb8 struct Init -> class Init 
Rename struct Init to class Init for consistency and in preparation
for making Init a FoldingSetNode.

llvm-svn: 135097
 2011-07-13 22:25:51 +00:00
Jakob Stoklund Olesen
5102a957a1 Revert r135074 and r135080. They broke clamscan. 
llvm-svn: 135096
 2011-07-13 22:20:09 +00:00
Jim Grosbach
d5e74991f0 Shuffle ARM assembly tests a bit. 
llvm-svn: 135095
 2011-07-13 22:19:10 +00:00
Jim Grosbach
c9e49f3b51 Revert 135093. Think-o. 
llvm-svn: 135094
 2011-07-13 22:06:11 +00:00
Jim Grosbach
545a3f4802 Correct range for thumb co-processor immediate 
llvm-svn: 135093
 2011-07-13 22:03:11 +00:00
Jim Grosbach
fd2ebb4552 Range checking for CDP[2] immediates. 
llvm-svn: 135092
 2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes
c0401dddf7 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more 
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

llvm-svn: 135088
 2011-07-13 21:36:51 +00:00
Bruno Cardoso Lopes
b98f50da03 The target specific node PANDN name is misleading. That happens because 
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.

llvm-svn: 135087
 2011-07-13 21:36:47 +00:00
Jim Grosbach
76ba2e7e9c Cleanup Thumb co-processor instructions a bit. 
Combine redundant base classes and such. No indended functional change.

llvm-svn: 135085
 2011-07-13 21:35:10 +00:00
Eli Friedman
30d557cc28 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. 
<rdar://problem/9763308>

llvm-svn: 135084
 2011-07-13 21:29:53 +00:00
Jim Grosbach
385d9a3e57 Parameterize away the ARM T1Cop class. 
llvm-svn: 135082
 2011-07-13 21:17:59 +00:00
Jim Grosbach
d3b15141b8 Fix predicates for Thumb co-processor instructions. 
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081
 2011-07-13 21:14:23 +00:00
Jakob Stoklund Olesen
db508ece2d Only keep the global split candidates that work out. 
Some pysical registers create split solutions that would spill anywhere.
They should not even be considered in future multi-way global splits.

This does not affect code generation (yet).

llvm-svn: 135080
 2011-07-13 20:49:46 +00:00
Eli Friedman
e0a117fbdf Refactor out checking for displacements on x86-64 addressing modes. No functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress. 
Part of <rdar://problem/9763308>.

llvm-svn: 135079
 2011-07-13 20:44:23 +00:00
Jim Grosbach
c7e0941dac Testcases for ARM assembly BX/BXJ instructions. 
llvm-svn: 135078
 2011-07-13 20:25:46 +00:00
Jim Grosbach
93cf7d8372 Fix encoding for ARM BXJ instruction. 
llvm-svn: 135077
 2011-07-13 20:25:01 +00:00
Jim Grosbach
4ca79b8d2c Fix encoding of predicate bits on ARM BX_pred. 
llvm-svn: 135076
 2011-07-13 20:21:31 +00:00
Jakob Stoklund Olesen
a1cd88cd42 Move the InterferenceCache cursor into the GlobalSplitCand struct. 
This is in preparation of supporting multiple global split candidates in
a single live range split operation.

llvm-svn: 135074
 2011-07-13 20:14:52 +00:00
Jim Grosbach
0313701671 Testcases for ARM assembly BLX/BL instructions. 
llvm-svn: 135072
 2011-07-13 20:11:04 +00:00
Jim Grosbach
0caa098513 Range checking for 16-bit immediates in ARM assembly. 
llvm-svn: 135071
 2011-07-13 20:10:10 +00:00
Jay Foad
857e1b2659 Revert r135042. As Chris pointed out, it had no effect, and was based on 
a complete misunderstanding of the code.

llvm-svn: 135070
 2011-07-13 20:05:31 +00:00
Evan Cheng
7bdc771798 Fix up TargetLoweringObjectFile ctors to properly initialize fields. 
llvm-svn: 135068
 2011-07-13 19:54:59 +00:00
Jim Grosbach
ab030d8a81 Give the ARM BKPT instruction the right operand type. 
The immediate is of limited range and the operand type should reflect that.

llvm-svn: 135066
 2011-07-13 19:24:09 +00:00
Evan Cheng
13c2a2dac3 Change test case, one that actually failed before my commit. 
llvm-svn: 135064
 2011-07-13 19:19:44 +00:00
Jim Grosbach
9e021b5281 Add tests for ARM parsing of 'BKPT' instruction. 
llvm-svn: 135063
 2011-07-13 19:17:36 +00:00
Jim Grosbach
ce9b6636b3 Fix copy-pasto. 
llvm-svn: 135062
 2011-07-13 19:16:30 +00:00
Jim Grosbach
9d1a4de9e6 Add tests for ARM parsing of 'BIC' instruction. 
llvm-svn: 135061
 2011-07-13 19:12:32 +00:00
Jim Grosbach
7aea4b177f Add some FIXMEs. 
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.

llvm-svn: 135060
 2011-07-13 19:10:23 +00:00
Evan Cheng
2b69573e57 Revert accidental commit. 
llvm-svn: 135059
 2011-07-13 19:09:08 +00:00
Evan Cheng
ba4a50f10c It's not safe to fold (fptrunc (sqrt (fpext x))) to (sqrtf x) if there is another use of sqrt. rdar://9763193 
llvm-svn: 135058
 2011-07-13 19:08:16 +00:00
Jim Grosbach
9b9604762e Add tests for ARM parsing of 'AND' instruction. 
llvm-svn: 135056
 2011-07-13 18:55:14 +00:00
Jim Grosbach
5c366bfb36 Improve ARM assembly parsing diagnostics a bit. 
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.

llvm-svn: 135055
 2011-07-13 18:49:30 +00:00
Jim Grosbach
a0a947a8ca Add tests for ARM parsing of 'ADD' instruction 
llvm-svn: 135053
 2011-07-13 18:12:46 +00:00
Jim Grosbach
7dbb39dffa Destination register operand is optional for ADC and SBC ARM. 
llvm-svn: 135052
 2011-07-13 17:57:17 +00:00
Jim Grosbach
5db1296fcd Flesh out ARM Parser support for shifted-register operands. 
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049
 2011-07-13 17:50:29 +00:00
Jim Grosbach
bcc9f6f31a 80 columns. 
llvm-svn: 135047
 2011-07-13 17:25:55 +00:00
Jim Grosbach
e0fc4019f9 Update MCParsedAsmOperand debug methods. 
Update the debug output interface for MCParsedAsmOperand to have a print()
method which takes an output stream argument, an << operator which invokes
the print method using the given stream, and a dump() method which prints
the operand to the dbgs() stream. This makes the interface more consistent
with the rest of LLVM, and more convenient to use at the debugger command
line.

llvm-svn: 135043
 2011-07-13 15:34:57 +00:00
Jay Foad
ca8c3afd77 Really cache function types and anonymous struct types. 
llvm-svn: 135042
 2011-07-13 10:39:49 +00:00
Jay Foad
88fb4f4597 Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef. 
llvm-svn: 135040
 2011-07-13 10:26:04 +00:00
Jay Foad
eaccc60d30 Add some bits that I found useful when converting InsertValueInst and 
ExtractValueInst APIs to use ArrayRef: a new constructor taking a
(begin, end) range, and operators == and != for element-wise comparison.

llvm-svn: 135039
 2011-07-13 09:15:05 +00:00
Danil Malyshev
e297cd5195 Add to RuntimeDyld support different object formats 
llvm-svn: 135037
 2011-07-13 07:57:58 +00:00
Chris Lattner
e299b86ead stop leaking all named struct types with an empty name. Thanks 
to Benjamin Kramer for steering me in the right direction here.

llvm-svn: 135031
 2011-07-13 04:22:39 +00:00
Evan Cheng
ddc415a907 Add an entry. 
llvm-svn: 135024
 2011-07-13 01:33:00 +00:00
Bruno Cardoso Lopes
cb49278ad6 AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd 
llvm-svn: 135023
 2011-07-13 01:15:33 +00:00