Nate Begeman
811a41a87c
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
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work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
Chris Lattner
89c435541a
Adjust to change in ctor
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llvm-svn: 23585
2005-10-02 06:23:51 +00:00
Chris Lattner
c744d9398f
Rename MRegisterDesc -> TargetRegisterDesc for consistency
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llvm-svn: 23564
2005-09-30 17:49:27 +00:00
Chris Lattner
661384dce6
trim down the target info structs now that we have a preferred spill register class for each callee save register
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Why is V9 maintaining these tables manually? ugh!
llvm-svn: 23561
2005-09-30 17:38:36 +00:00
Chris Lattner
a1266f8ed5
Pass extra regclasses into spilling code
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llvm-svn: 23537
2005-09-30 01:29:42 +00:00
Misha Brukman
1fef885677
Remove trailing whitespace
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llvm-svn: 21425
2005-04-21 23:30:14 +00:00
Chris Lattner
555a585fd8
Code insertion methods now return void instead of an int.
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llvm-svn: 15780
2004-08-15 22:15:11 +00:00
Chris Lattner
e58190f5f6
These methods no longer take a TargetRegisterClass* operand.
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llvm-svn: 15774
2004-08-15 21:56:44 +00:00
Nate Begeman
edeb64e748
Eliminate MachineFunction& argument from eliminateFrameIndex in SparcV9 target
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llvm-svn: 15738
2004-08-14 22:03:29 +00:00
Brian Gaeke
a36743c473
Add MRegisterInfo subclass for the SparcV9 target (containing only stub
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functions for now). This automatically turns on the printing of machine
registers using their own real names, instead of goofy things like %mreg(42),
and allows us to migrate code incrementally to the new interface as we see fit.
The register file description it uses is hand-written, so that the register
numbers will match the ones that the SparcV9 target already uses.
Perhaps someday we'll tablegen it.
llvm-svn: 13145
2004-04-25 06:32:05 +00:00
