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Commit Graph

102 Commits

Author SHA1 Message Date
Benjamin Kramer
89ebc7ab4b Simplify some uses of utohexstr.
As a side effect hex is printed lowercase instead of uppercase now.

llvm-svn: 144013
2011-11-07 21:00:59 +00:00
Daniel Dunbar
3760ebeebb build: Add initial cut at LLVMBuild.txt files.
llvm-svn: 143634
2011-11-03 18:53:17 +00:00
Owen Anderson
ac9fd95057 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
llvm-svn: 143557
2011-11-02 18:03:14 +00:00
Jim Grosbach
68dfc88f95 Assembly parsing for 4-register variant of VLD1.
llvm-svn: 142682
2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9 Assembly parsing for 3-register variant of VLD1.
llvm-svn: 142675
2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97 ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
2011-10-21 18:54:25 +00:00
Jim Grosbach
a1d54f2c7a whitespace.
llvm-svn: 142657
2011-10-21 16:56:40 +00:00
Jim Grosbach
6a932d6ad1 ARM VTBL (one register) assembly parsing and encoding.
llvm-svn: 142441
2011-10-18 23:02:30 +00:00
Jim Grosbach
eb7acc978a ARM parsing and encoding for the <option> form of LDC/STC instructions.
llvm-svn: 141786
2011-10-12 17:34:41 +00:00
Jim Grosbach
70a91e2da7 80 columns.
llvm-svn: 141781
2011-10-12 16:36:01 +00:00
Jim Grosbach
3b205dab2d Tidy up. Formatting.
llvm-svn: 141780
2011-10-12 16:34:37 +00:00
Jim Grosbach
94980a23e6 ARM NEON assembly parsing and encoding for VDUP(scalar).
llvm-svn: 141446
2011-10-07 23:56:00 +00:00
Owen Anderson
2d1e930b65 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
llvm-svn: 141190
2011-10-05 17:16:40 +00:00
Kevin Enderby
5a09a8db55 Adding back support for printing operands symbolically to ARM's new disassembler
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 141129
2011-10-04 22:44:48 +00:00
Jim Grosbach
d94ffffc87 ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
2011-09-30 00:50:06 +00:00
James Molloy
c4fcff419c Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696
2011-09-28 14:21:38 +00:00
Owen Anderson
53c6b08ad8 Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
llvm-svn: 140420
2011-09-23 21:26:40 +00:00
Owen Anderson
22ab29756b Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
llvm-svn: 140284
2011-09-21 23:53:44 +00:00
Owen Anderson
7b134fe54c Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.
llvm-svn: 140283
2011-09-21 23:44:46 +00:00
Owen Anderson
220db2953c These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
llvm-svn: 140267
2011-09-21 17:58:45 +00:00
Owen Anderson
fbec62c99e In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
llvm-svn: 140217
2011-09-21 00:25:23 +00:00
Jim Grosbach
6da9e6b23d Thumb2 assembly parsing and encoding for TBB/TBH.
llvm-svn: 140078
2011-09-19 22:21:13 +00:00
Owen Anderson
5804085f26 Fix disassembly of Thumb2 LDRSH with a #-0 offset.
llvm-svn: 139943
2011-09-16 21:08:33 +00:00
Owen Anderson
e54c4beb5a Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
llvm-svn: 139876
2011-09-15 23:38:46 +00:00
Owen Anderson
84d4e5d0e2 Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode.
llvm-svn: 139820
2011-09-15 18:36:29 +00:00
Owen Anderson
d0121fe635 Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
llvm-svn: 139639
2011-09-13 20:46:26 +00:00
Jim Grosbach
eb2d668899 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
llvm-svn: 139381
2011-09-09 18:37:27 +00:00
James Molloy
f781d3d8e9 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
llvm-svn: 139237
2011-09-07 17:24:38 +00:00
Owen Anderson
e14d6edccc Improve handling of #-0 offsets for many more pre-indexed addressing modes.
llvm-svn: 138754
2011-08-29 19:36:44 +00:00
Jim Grosbach
ccee1ff0f5 When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
rdar://10015134

llvm-svn: 138467
2011-08-24 20:06:14 +00:00
Jim Grosbach
6ada94c011 Clean up Thumb load/store multiple definitions.
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.

llvm-svn: 138338
2011-08-23 17:41:15 +00:00
Jim Grosbach
be94868d66 Thumb parsing and encoding support for NOP.
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
2011-08-19 23:24:36 +00:00
Jim Grosbach
7ecefeb594 Thumb assembly parsing and encoding for LDM instruction.
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
2011-08-18 21:50:53 +00:00
Jim Grosbach
ed7d35c932 Remove extraneous newline from operand print method. PR10569.
llvm-svn: 137900
2011-08-17 23:23:07 +00:00
Jim Grosbach
3efc45bfad ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.

llvm-svn: 137879
2011-08-17 21:51:27 +00:00
Owen Anderson
707fcaca0e Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
Jim Grosbach
9717a9c0d3 ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
2011-08-11 18:07:11 +00:00
Jim Grosbach
abaaf4513f ARM pop of a single register encodes as post-indexed LDR.
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
2011-08-11 17:35:48 +00:00
Jim Grosbach
67621a1af4 ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

llvm-svn: 136969
2011-08-05 16:11:38 +00:00
Jim Grosbach
e89ee8ab6e ARM use a dedicated printer for postidx_reg operands.
llvm-svn: 136968
2011-08-05 15:48:21 +00:00
Owen Anderson
1136bcc11e LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
llvm-svn: 136896
2011-08-04 18:24:14 +00:00
Jim Grosbach
767e9d16e6 ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Chandler Carruth
f7890e34b9 Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

llvm-svn: 136433
2011-07-29 00:14:25 +00:00
Jim Grosbach
23c317b5a1 ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.

llvm-svn: 136154
2011-07-26 21:44:37 +00:00
Jim Grosbach
24aa0e7c2e ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.

llvm-svn: 136152
2011-07-26 21:28:43 +00:00
Chandler Carruth
a571c5d5d3 Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.

These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.

To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.

This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.

Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.

llvm-svn: 136023
2011-07-26 00:09:08 +00:00
Jim Grosbach
ef3d573e31 ARM assembly parsing and encoding for SSAT16 instruction.
llvm-svn: 136006
2011-07-25 23:09:14 +00:00
Jim Grosbach
c1fe042da0 ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.

llvm-svn: 135990
2011-07-25 22:20:28 +00:00
Evan Cheng
41aa34c417 Sink ARM mc routines into MCTargetDesc.
llvm-svn: 135825
2011-07-23 00:00:19 +00:00
Jim Grosbach
dd6b9fa0da ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.

llvm-svn: 135823
2011-07-22 23:16:18 +00:00