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Commit Graph

63278 Commits

Author SHA1 Message Date
David Blaikie
d801507700 DebugInfo: Prefer references over pointers, pass by const reference for a type that will grow in the future
llvm-svn: 188422
2013-08-14 22:23:05 +00:00
Tom Stellard
6287532c80 R600/SI: Handle MSAA texture targets
Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188421
2013-08-14 22:22:14 +00:00
Tom Stellard
5d16e4f78e R600/SI: Allow conversion between v32i8 and v8i32
Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188420
2013-08-14 22:22:09 +00:00
Tom Stellard
9ea351d77c R600/SI: Fix an obvious typo
Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188419
2013-08-14 22:22:03 +00:00
Tom Stellard
9e2fd5271f R600/SI: Add pattern for fp_to_uint
This fixes the F2U opcode for the Mesa driver.

Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188418
2013-08-14 22:21:57 +00:00
Mark Lacey
c3ab3bb4bc Fix small typo: s/succ/Succ/
llvm-svn: 188415
2013-08-14 22:11:42 +00:00
Peter Collingbourne
8968732c46 DataFlowSanitizer: Instrumentation for memset.
Differential Revision: http://llvm-reviews.chandlerc.com/D1395

llvm-svn: 188412
2013-08-14 20:51:38 +00:00
Hal Finkel
a89d228510 Actually fix PPC64 64-bit GPR inline asm constraint matching
This is a follow-up to r187693, correcting that code to request the correct
register class. The previous version, with the wrong register class, was not
really correcting the constraints, but rather was removing them. Coincidentally,
this fixed the failing test case in r187693, but obviously created other
problems.

llvm-svn: 188407
2013-08-14 20:05:04 +00:00
Peter Collingbourne
905e1efbe5 DataFlowSanitizer: greylist is now ABI list.
This replaces the old incomplete greylist functionality with an ABI
list, which can provide more detailed information about the ABI and
semantics of specific functions.  The pass treats every function in
the "uninstrumented" category in the ABI list file as conforming to
the "native" (i.e. unsanitized) ABI.  Unless the ABI list contains
additional categories for those functions, a call to one of those
functions will produce a warning message, as the labelling behaviour
of the function is unknown.  The other supported categories are
"functional", "discard" and "custom".

- "discard" -- This function does not write to (user-accessible) memory,
  and its return value is unlabelled.
- "functional" -- This function does not write to (user-accessible)
  memory, and the label of its return value is the union of the label of
  its arguments.
- "custom" -- Instead of calling the function, a custom wrapper __dfsw_F
  is called, where F is the name of the function.  This function may wrap
  the original function or provide its own implementation.

Differential Revision: http://llvm-reviews.chandlerc.com/D1345

llvm-svn: 188402
2013-08-14 18:54:12 +00:00
Reid Kleckner
fbab94162c Use the MSVC __cpuid intrinsic instead of inline asm
This works around PR16830 in LLVM when self-hosting clang on Windows.

llvm-svn: 188397
2013-08-14 18:21:51 +00:00
Jakob Stoklund Olesen
18768bf820 Remove unnecessary parameter to RenumberValues.
Patch by Matthias Braun!

llvm-svn: 188393
2013-08-14 17:28:52 +00:00
Jakob Stoklund Olesen
30b3d9b0e1 Improve misleading comment.
Patch by Matthias Braun!

llvm-svn: 188391
2013-08-14 17:28:46 +00:00
Jakob Stoklund Olesen
28d8a03220 Remove declaration of nonexistant function.
Patch by Matthias Braun!

llvm-svn: 188390
2013-08-14 17:28:44 +00:00
Jakob Stoklund Olesen
63c72237a7 LiveIntervalUnion is not used in RegAllocBase.
Patch by Matthias Braun!

llvm-svn: 188389
2013-08-14 17:28:42 +00:00
Renato Golin
5068d4579d Let t2LDRBi8 and t2LDRBi12 have same Base Pointer
When determining if two different loads are from the same base address,
this patch allows one load to use a t2LDRi8 address mode and another to
use a t2LDRi12 address mode. The current implementation is very
conservative and this allows the case of differing Thumb2 byte loads to
be considered. Allowing these differing modes instead of forcing the exact
same opcode is useful for situations where one opcodes loads from a base
address+1 and a second opcode loads for a base address-1.

Patch by Daniel Stewart.

llvm-svn: 188385
2013-08-14 16:35:29 +00:00
Alexey Samsonov
235b9a341c Expose CRC-32 implementation from zlib
llvm-svn: 188380
2013-08-14 16:03:29 +00:00
Tim Northover
c40d142f19 Support C99 hexadecimal floating-point literals in assembly
It's useful to be able to write down floating-point numbers without having to
worry about what they'll be rounded to (as C99 discovered), this extends that
ability to the MC assembly parsers.

llvm-svn: 188370
2013-08-14 14:23:31 +00:00
Chandler Carruth
219c3d81d0 Fix a really terrifying but improbable bug in mem2reg. If you have seen
extremely subtle miscompilations (such as a load getting replaced with
the value stored *below* the load within a basic block) related to
promoting an alloca to an SSA value, there is the dim possibility that
you hit this. Please let me know if you won this unfortunate lottery.

The first half of mem2reg's core logic (as it is used both in the
standalone mem2reg pass and in SROA) builds up a mapping from
'Instruction *' to the index of that instruction within its basic block.
This allows quickly establishing which store dominate a particular load
even for large basic blocks. We cache this information throughout the
run of mem2reg over a function in order to amortize the cost of
computing it.

This is not in and of itself a strange pattern in LLVM. However, it
introduces a very important constraint: absolutely no instruction can be
deleted from the program without updating the mapping. Otherwise a newly
allocated instruction might get the same pointer address, and then end
up with a wrong index. Yes, LLVM routinely suffers from a *single
threaded* variant of the ABA problem. Most places in LLVM don't find
avoiding this an imposition because they don't both delete and create
new instructions iteratively, but mem2reg *loves* to do this... All the
time. Fortunately, the mem2reg code was really careful about updating
this cache to handle this eventuallity... except when it comes to the
debug declare intrinsic. Oops. The fix is to invalidate that pointer in
the cache when we delete it, the same as we do when deleting alloca
instructions and other instructions.

I've also caused the same bug in new code while working on a fix to
PR16867, so this seems to be a really unfortunate pattern. Hopefully in
subsequent patches the deletion of dead instructions can be consolidated
sufficiently to make it less likely that we'll see future occurences of
this bug.

Sorry for not having a test case, but I have literally no idea how to
reliably trigger this kind of thing. It may be single-threaded, but it
remains an ABA problem. It would require a really amazing number of
stars to align.

llvm-svn: 188367
2013-08-14 08:56:41 +00:00
Craig Topper
6098714945 Make more helper methods into static functions.
llvm-svn: 188366
2013-08-14 07:53:41 +00:00
Craig Topper
6104601f38 Remove tab characters.
llvm-svn: 188365
2013-08-14 07:35:18 +00:00
Craig Topper
c13ba6b595 Make some helper methods static.
llvm-svn: 188364
2013-08-14 07:34:43 +00:00
Craig Topper
ea9da24130 Use MVT in more lowering code.
llvm-svn: 188363
2013-08-14 07:04:42 +00:00
Craig Topper
6785f01079 Replace EVT with MVT in isVectorShift. Keeps compiler from generating unneeded checks and handling for extended types.
llvm-svn: 188362
2013-08-14 06:21:10 +00:00
Craig Topper
be2cc9fc41 Replace EVT with MVT in many of the shuffle lowering functions. Keeps compiler from generating unneeded checks and handling for extended types.
llvm-svn: 188361
2013-08-14 05:58:39 +00:00
Akira Hatanaka
6a7f10d027 [mips] Fix bug in parsing accumulator registers.
llvm-svn: 188344
2013-08-14 01:15:52 +00:00
Akira Hatanaka
2f7e9a3a07 [mips] Use register operands instead of register classes in DSP instruction
definitions.

llvm-svn: 188343
2013-08-14 01:02:20 +00:00
Akira Hatanaka
3e7c555daa [mips] Rename DSPRegs.
llvm-svn: 188342
2013-08-14 00:53:38 +00:00
Akira Hatanaka
6ac16b554b [mips] Rename HIRegs and LORegs.
llvm-svn: 188341
2013-08-14 00:47:08 +00:00
Matt Arsenault
cb3b478d91 Fix always creating GEP with i32 indices
Use the pointer size if datalayout is available.
Use i64 if it's not, which is consistent with what other
places do when the pointer size is unknown.

The test doesn't really test this in a useful way
since it will be transformed to that later anyway,
but this now tests it for non-zero arrays and when
datalayout isn't available. The cases in
visitGetElementPtrInst should save an extra re-visit to
the newly created GEP since it won't need to cleanup after
itself.

llvm-svn: 188339
2013-08-14 00:24:38 +00:00
Matt Arsenault
6d1daebfff Use type helper functions instead of cast
llvm-svn: 188338
2013-08-14 00:24:34 +00:00
Matt Arsenault
734103e561 Use array initializer, space around operator
llvm-svn: 188337
2013-08-14 00:24:05 +00:00
Akira Hatanaka
ff296075bc [mips] Properly parse registers that appear in inline-asm constraints.
llvm-svn: 188336
2013-08-14 00:21:25 +00:00
Hal Finkel
fd36621506 BBVectorize: Add initial stores to the write set when tracking uses
When computing the use set of a store, we need to add the store to the write
set prior to iterating over later instructions. Otherwise, if there is a later
aliasing load of that store, that load will not be tagged as a use, and bad
things will happen.

trackUsesOfI still adds later dependent stores of an instruction to that
instruction's write set, but it never sees the original instruction, and so
when tracking uses of a store, the store must be added to the write set by the
caller.

Fixes PR16834.

llvm-svn: 188329
2013-08-13 23:34:32 +00:00
Nick Lewycky
eab287a60a Revert r187191, which broke opt -mem2reg on the testcases included in PR16867.
However, opt -O2 doesn't run mem2reg directly so nobody noticed until r188146
when SROA started sending more things directly down the PromoteMemToReg path.

In order to revert r187191, I also revert dependent revisions r187296, r187322
and r188146. Fixes PR16867. Does not add the testcases from that PR, but both
of them should get added for both mem2reg and sroa when this revert gets
unreverted.

llvm-svn: 188327
2013-08-13 22:51:58 +00:00
Jack Carter
15a173ab4f [Mips][msa] Value types for MSA support.
Added v8f16 to ValueTypes.h, ValueTypes.cpp, ValueTypes.td, 
and CodeGenTarget.cpp

Patch by Daniel Sanders

llvm-svn: 188326
2013-08-13 22:34:26 +00:00
Hans Wennborg
581964696d Options: explicit handling of --
Clients of the option parsing library should handle it explicitly
using a KIND_REMAINING_ARGS option.

Clang and lld have been updated in r188316 and r188318, respectively.

Also fix -Wsign-compare warning in the option parsing test.

llvm-svn: 188323
2013-08-13 22:23:05 +00:00
Jim Grosbach
a6bd8c2220 DAG: Combine (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
A common idiom is to use zero and all-ones as sentinal values and to
check for both in a single conditional ("x != 0 && x != (unsigned)-1").
That generates code, for i32, like:
  testl %edi, %edi
  setne %al
  cmpl  $-1, %edi
  setne %cl
  andb  %al, %cl

With this transform, we generate the simpler:
  incl  %edi
  cmpl  $1, %edi
  seta  %al

Similar improvements for other integer sizes and on other platforms. In
general, combining the two setcc instructions into one is better.

rdar://14689217

llvm-svn: 188315
2013-08-13 21:30:58 +00:00
Hans Wennborg
714e82ffc5 Options: Add new option kind that consumes remaining arguments
This adds KIND_REMAINING_ARGS, a class of options that consume
all remaining arguments on the command line.

This will be used to support /link in clang-cl, which is used
to forward all remaining arguments to the linker.

It also allows us to remove the hard-coded handling of "--",
allowing clients (clang and lld) to implement that functionality
themselves with this new option class.

Differential Revision: http://llvm-reviews.chandlerc.com/D1387

llvm-svn: 188314
2013-08-13 21:09:50 +00:00
Jack Carter
da7e928e92 [Mips][msa] Added initial MSA support.
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions

Does not correctly prohibit use of both 32-bit FPU registers and MSA together.

Patch by Daniel Sanders

llvm-svn: 188313
2013-08-13 20:54:07 +00:00
Jack Carter
cb8856c2c6 [Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic

llvm-svn: 188312
2013-08-13 20:19:16 +00:00
Michael Gottesman
30dcd21864 Update makeLibCall to return both the call and the chain associated with the libcall instead of just the call. This allows us to specify libcalls that return void.
LowerCallTo returns a pair with the return value of the call as the first
element and the chain associated with the return value as the second element. If
we lower a call that has a void return value, LowerCallTo returns an SDValue
with a NULL SDNode and the chain for the call. Thus makeLibCall by just
returning the first value makes it impossible for you to set up the chain so
that the call is not eliminated as dead code.

I also updated all references to makeLibCall to reflect the new return type.

llvm-svn: 188300
2013-08-13 17:54:56 +00:00
Carlo Kok
1b6e9cea0f Output DW_AT_stmt_list dwarf debug info as DW_FORM_sec_offset instead of DW_FORM_data4 as it is a section offset (fixes the coff/dwarf debug info statement locations)
llvm-svn: 188297
2013-08-13 17:46:57 +00:00
Carlo Kok
d10cf40934 For COFF only: dwarf debug info output a label reference as a section relative item only when it's one of dw_from strp, sec_offset, ref_addr or op_call_ref instead of going by size.
llvm-svn: 188296
2013-08-13 17:45:53 +00:00
Dmitry Vyukov
fe91b1efa2 dfsan: fix lint warnings
llvm-svn: 188293
2013-08-13 16:52:41 +00:00
Joey Gouly
c5221430a1 ARMv8: SWP and SWPB are obsoleted on ARMv8.
llvm-svn: 188288
2013-08-13 16:40:47 +00:00
Arnold Schwaighofer
dfaac373ee Also remove logic in LateVectorize
llvm-svn: 188285
2013-08-13 16:12:04 +00:00
Arnold Schwaighofer
406976609b Remove logic that decides whether to vectorize or not depending on O-levels
I have moved this logic into clang and opt.

llvm-svn: 188281
2013-08-13 15:51:25 +00:00
Evgeniy Stepanov
0caff76271 Fix compiler warnings.
../lib/Target/X86/X86ISelLowering.cpp:9715:7: error: unused variable 'OpVT' [-Werror,-Wunused-variable]
  EVT OpVT = Op0.getValueType();
      ^
../lib/Target/X86/X86ISelLowering.cpp:9763:14: error: unused variable 'NumElems' [-Werror,-Wunused-variable]
    unsigned NumElems = VT.getVectorNumElements();

llvm-svn: 188269
2013-08-13 14:04:20 +00:00
Mihai Popa
f30d3c418d Fix signed overflow in when computing encodings for ADR instructions
llvm-svn: 188268
2013-08-13 14:02:13 +00:00
Elena Demikhovsky
42b33ee116 AVX-512: Added CMP and BLEND instructions.
Lowering for SETCC.

llvm-svn: 188265
2013-08-13 13:24:07 +00:00