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Commit Graph

9 Commits

Author SHA1 Message Date
Jim Grosbach
f3bd81ce11 Clean up 80 column violations. No functional change.
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Jakob Stoklund Olesen
ac6f519e79 Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h

llvm-svn: 104508
2010-05-24 16:54:32 +00:00
Evan Cheng
d43aee655d Expand VMOVQQ into a pair of VMOVQ.
llvm-svn: 103684
2010-05-13 00:17:02 +00:00
Evan Cheng
aef4fc8804 Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.
llvm-svn: 103667
2010-05-12 23:13:12 +00:00
Evan Cheng
fe02735100 Remove a dead fixme.
llvm-svn: 103642
2010-05-12 20:20:22 +00:00
Dan Gohman
0e0b8cf9fd Add const qualifiers to CodeGen's use of LLVM IR constructs.
llvm-svn: 101334
2010-04-15 01:51:59 +00:00
Chris Lattner
9ce833945e improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!

llvm-svn: 90365
2009-12-03 00:50:42 +00:00
Anton Korobeynikov
0f885eb7fd Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
2009-11-24 00:44:37 +00:00
Evan Cheng
6e3e66375a - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
2009-11-06 23:52:48 +00:00