RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 13:33:37 +02:00
Code Issues Projects Releases Wiki Activity
14,688 Commits 4 Branches 5 Tags 704 MiB
f8380b953a
Commit Graph

2296 Commits

Author SHA1 Message Date
Misha Brukman
995af8d2b1 Add ModuloScheduling to the recursive build tree 
llvm-svn: 16905
 2004-10-10 23:36:09 +00:00
Misha Brukman
95cbabd1b5 Adjust header file inclusion due to move 
llvm-svn: 16904
 2004-10-10 23:34:50 +00:00
Misha Brukman
0f102f7fc9 Adjust comment header and paths to refect move 
llvm-svn: 16903
 2004-10-10 23:34:36 +00:00
Misha Brukman
020c3ab94c ModuloScheduling moved to lib/Target/SparcV9 as it is SparcV9-specific 
llvm-svn: 16902
 2004-10-10 23:33:20 +00:00
Reid Spencer
85d2758f11 Initial version of automake Makefile.am file. 
llvm-svn: 16898
 2004-10-10 22:52:14 +00:00
Reid Spencer
04cb07f3ce Add the new InstrSched directory. 
llvm-svn: 16897
 2004-10-10 22:51:03 +00:00
Reid Spencer
1b7459b29d Initial version of automake Makefile.am file. 
llvm-svn: 16893
 2004-10-10 22:20:40 +00:00
Brian Gaeke
26b353ebd6 Fix assertion failure when calling or returning from a function which 
returns 'bool' type.

llvm-svn: 16884
 2004-10-10 20:34:17 +00:00
Brian Gaeke
3af0547680 Implement eliminateCallFramePseudoInstr(). 
Wrap a long comment line.

llvm-svn: 16883
 2004-10-10 19:57:21 +00:00
Brian Gaeke
b6239cd5ed Model calls as *both* using *and* killing O0..O5, because callees use the 
argument values passed in (so they're not dead until *after* the call),
and callees are free to modify those registers.

llvm-svn: 16882
 2004-10-10 19:57:20 +00:00
Brian Gaeke
245a073aa6 Fix whitespace and wrap some long lines. 
Deal with allocating stack space for outgoing args and copying them into the
correct stack slots (at least, we can copy <=32-bit int args).
We now correctly generate ADJCALLSTACK* instructions.

llvm-svn: 16881
 2004-10-10 19:57:18 +00:00
Chris Lattner
6ff0fd4837 bling bling! 
llvm-svn: 16873
 2004-10-10 16:26:13 +00:00
Chris Lattner
955a220ad2 Instead of silently breaking, print notification of why this doesn't work. 
llvm-svn: 16870
 2004-10-09 21:13:51 +00:00
Brian Gaeke
ba13791a01 update according to tonight's info 
llvm-svn: 16866
 2004-10-09 05:58:27 +00:00
Brian Gaeke
3abdd11420 Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the 
default 32/BE target on sparc hosts, and ppc will continue to be the default
on other hosts.

llvm-svn: 16865
 2004-10-09 05:57:01 +00:00
Chris Lattner
2419e1d27e The person who was planning to add SSE support isn't anymore, so disable 
the -sse* options (to avoid misleading people).

Also, the stack alignment of the target doesn't depend on whether SSE is
eventually implemented, so remove a comment.

llvm-svn: 16860
 2004-10-08 22:41:46 +00:00
Chris Lattner
1291307d27 Fix a major regression from the bugfix for 2004-10-08-SelectSetCCFold.llx, 
which prevented setcc's from being folded into branches.  It appears that
conditional branchinst's CC operand is actually operand(2), not operand(0)
as we might expect. :(

llvm-svn: 16859
 2004-10-08 22:24:31 +00:00
Misha Brukman
d858079005 Adjust paths due to moving InstrSched to lib/Target/SparcV9 
llvm-svn: 16852
 2004-10-08 18:30:22 +00:00
Misha Brukman
049f559995 InstrSched is SparcV9-specific and so has been moved to lib/Target/SparcV9/ 
llvm-svn: 16849
 2004-10-08 18:12:14 +00:00
Misha Brukman
b1851ac70c Single-space instead of double-spacing in the Makefile 
llvm-svn: 16848
 2004-10-08 18:11:14 +00:00
Misha Brukman
cfe86b257b Build InstrSched as well, and all three subdirs can be built independently 
llvm-svn: 16847
 2004-10-08 18:10:48 +00:00
Chris Lattner
1ac1e54bf9 Fix bug: 2004-10-08-SelectSetCCFold.llx. Normally this is hidden by the 
instcombine xform, which is why we didn't notice it before.

llvm-svn: 16840
 2004-10-08 16:34:13 +00:00
Nate Begeman
dfefd2f3fc Implement logical and with an immediate that consists of a contiguous block 
of one or more 1 bits (may wrap from least significant bit to most
significant bit) as the rlwinm rather than andi., andis., or some longer
instructons sequence.

int andn4(int z) { return z & -4; }
int clearhi(int z) { return z & 0x0000FFFF; }
int clearlo(int z) { return z & 0xFFFF0000; }
int clearmid(int z) { return z & 0x00FFFF00; }
int clearwrap(int z) { return z & 0xFF0000FF; }

_andn4:
        rlwinm r3, r3, 0, 0, 29
        blr

_clearhi:
        rlwinm r3, r3, 0, 16, 31
        blr

_clearlo:
        rlwinm r3, r3, 0, 0, 15
        blr

_clearmid:
        rlwinm r3, r3, 0, 8, 23
        blr

_clearwrap:
        rlwinm r3, r3, 0, 24, 7
        blr

llvm-svn: 16832
 2004-10-08 02:49:24 +00:00
Nate Begeman
370b1b7a9a Several fixes and enhancements to the PPC32 backend. 
1. Fix an illegal argument to getClassB when deciding whether or not to
   sign extend a byte load.

2. Initial addition of isLoad and isStore flags to the instruction .td file
   for eventual use in a scheduler.

3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
   that we can emit the PowerPC shifted immediate instructions far more
   often.  This allows us to emit the following code:

int foo(int x) { return x | 0x00F0000; }

_foo:
.LBB_foo_0:     ; entry
        ; IMPLICIT_DEF
        oris r3, r3, 15
        blr

llvm-svn: 16826
 2004-10-07 22:30:03 +00:00
Nate Begeman
76d2a77998 Add ori reg, reg, 0 as a move instruction. This can be generated from 
loading a 32bit constant into a register whose low halfword is all zeroes.

We now omit the ori after the lis for the following C code:

int bar(int y) { return y * 0x00F0000; }

_bar:
.LBB_bar_0:     ; entry
        ; IMPLICIT_DEF
        lis r2, 15
        mullw r3, r3, r2
        blr

llvm-svn: 16825
 2004-10-07 22:26:12 +00:00
Nate Begeman
f60feea650 Remove unnecessary header include 
llvm-svn: 16824
 2004-10-07 22:24:32 +00:00
Chris Lattner
38fbf09104 Correct some typeos 
llvm-svn: 16770
 2004-10-06 16:28:24 +00:00
Chris Lattner
82aa8544a5 Remove debugging code, fix encoding problem. This fixes the problems 
the JIT had last night.

llvm-svn: 16766
 2004-10-06 14:31:50 +00:00
Nate Begeman
79d42a185e Turning on fsel code gen now that we can do so would be good. 
llvm-svn: 16765
 2004-10-06 11:03:30 +00:00
Nate Begeman
7b4fe83ba8 Implement floating point select for lt, gt, le, ge using the powerpc fsel 
instruction.

Now, rather than emitting the following loop out of bisect:
.LBB_main_19:	; no_exit.0.i
	rlwinm r3, r2, 3, 0, 28
	lfdx f1, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f2, f2, f1
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
	fcmpu cr0, f1, f4
	bge .LBB_main_64	; no_exit.0.i
.LBB_main_63:	; no_exit.0.i
	b .LBB_main_65	; no_exit.0.i
.LBB_main_64:	; no_exit.0.i
	fmr f2, f1
.LBB_main_65:	; no_exit.0.i
	addi r3, r2, 1
	rlwinm r3, r3, 3, 0, 28
	lfdx f1, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f4, f4, f1
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3)
	fcmpu cr0, f1, f5
	bge .LBB_main_67	; no_exit.0.i
.LBB_main_66:	; no_exit.0.i
	b .LBB_main_68	; no_exit.0.i
.LBB_main_67:	; no_exit.0.i
	fmr f4, f1
.LBB_main_68:	; no_exit.0.i
	fadd f1, f2, f4
	addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
	lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
	fmul f1, f1, f2
	rlwinm r3, r2, 3, 0, 28
	lfdx f2, r3, r28
	fadd f4, f2, f1
	fcmpu cr0, f4, f0
	bgt .LBB_main_70	; no_exit.0.i
.LBB_main_69:	; no_exit.0.i
	b .LBB_main_71	; no_exit.0.i
.LBB_main_70:	; no_exit.0.i
	fmr f0, f4
.LBB_main_71:	; no_exit.0.i
	fsub f1, f2, f1
	addi r2, r2, -1
	fcmpu cr0, f1, f3
	blt .LBB_main_73	; no_exit.0.i
.LBB_main_72:	; no_exit.0.i
	b .LBB_main_74	; no_exit.0.i
.LBB_main_73:	; no_exit.0.i
	fmr f3, f1
.LBB_main_74:	; no_exit.0.i
	cmpwi cr0, r2, -1
	fmr f16, f0
	fmr f17, f3
	bgt .LBB_main_19	; no_exit.0.i

We emit this instead:
.LBB_main_19:	; no_exit.0.i
	rlwinm r3, r2, 3, 0, 28
	lfdx f1, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f2, f2, f1
	fsel f1, f1, f1, f2
	addi r3, r2, 1
	rlwinm r3, r3, 3, 0, 28
	lfdx f2, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f4, f4, f2
	fsel f2, f2, f2, f4
	fadd f1, f1, f2
	addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
	lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
	fmul f1, f1, f2
	rlwinm r3, r2, 3, 0, 28
	lfdx f2, r3, r28
	fadd f4, f2, f1
	fsub f5, f0, f4
	fsel f0, f5, f0, f4
	fsub f1, f2, f1
	addi r2, r2, -1
	fsub f2, f1, f3
	fsel f3, f2, f3, f1
	cmpwi cr0, r2, -1
	fmr f16, f0
	fmr f17, f3
	bgt .LBB_main_19	; no_exit.0.i

llvm-svn: 16764
 2004-10-06 09:53:04 +00:00
Chris Lattner
b0e465f0cb Codegen signed mod by 2 or -2 more efficiently. Instead of generating: 
t:
        mov %EDX, DWORD PTR [%ESP + 4]
        mov %ECX, 2
        mov %EAX, %EDX
        sar %EDX, 31
        idiv %ECX
        mov %EAX, %EDX
        ret

Generate:
t:
        mov %ECX, DWORD PTR [%ESP + 4]
***     mov %EAX, %ECX
        cdq
        and %ECX, 1
        xor %ECX, %EDX
        sub %ECX, %EDX
***     mov %EAX, %ECX
        ret

Note that the two marked moves are redundant, and should be eliminated by the
register allocator, but aren't.

Compare this to GCC, which generates:

t:
        mov     %eax, DWORD PTR [%esp+4]
        mov     %edx, %eax
        shr     %edx, 31
        lea     %ecx, [%edx+%eax]
        and     %ecx, -2
        sub     %eax, %ecx
        ret

or ICC 8.0, which generates:

t:
        movl      4(%esp), %ecx                                 #3.5
        movl      $-2147483647, %eax                            #3.25
        imull     %ecx                                          #3.25
        movl      %ecx, %eax                                    #3.25
        sarl      $31, %eax                                     #3.25
        addl      %ecx, %edx                                    #3.25
        subl      %edx, %eax                                    #3.25
        addl      %eax, %eax                                    #3.25
        negl      %eax                                          #3.25
        subl      %eax, %ecx                                    #3.25
        movl      %ecx, %eax                                    #3.25
        ret                                                     #3.25

We would be in great shape if not for the moves.

llvm-svn: 16763
 2004-10-06 05:01:07 +00:00
Chris Lattner
c959314701 Really fix FreeBSD, which apparently doesn't tolerate the extern. 
Thanks to Jeff Cohen for pointing out my goof.

llvm-svn: 16762
 2004-10-06 04:21:52 +00:00
Chris Lattner
09b6b3f514 Fix a scary bug with signed division by a power of two. We used to generate: 
s:   ;; X / 4
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        sar %ECX, 1
        shr %ECX, 30
        mov %EDX, %EAX
        add %EDX, %ECX
        sar %EAX, 2
        ret

When we really meant:

s:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        sar %ECX, 1
        shr %ECX, 30
        add %EAX, %ECX
        sar %EAX, 2
        ret

Hey, this also reduces register pressure too :)

llvm-svn: 16761
 2004-10-06 04:19:43 +00:00
Chris Lattner
9258948b08 Codegen signed divides by 2 and -2 more efficiently. In particular 
instead of:

s:   ;; X / 2
        movl 4(%esp), %eax
        movl %eax, %ecx
        shrl $31, %ecx
        movl %eax, %edx
        addl %ecx, %edx
        sarl $1, %eax
        ret

t:   ;; X / -2
        movl 4(%esp), %eax
        movl %eax, %ecx
        shrl $31, %ecx
        movl %eax, %edx
        addl %ecx, %edx
        sarl $1, %eax
        negl %eax
        ret

Emit:

s:
        movl 4(%esp), %eax
        cmpl $-2147483648, %eax
        sbbl $-1, %eax
        sarl $1, %eax
        ret

t:
        movl 4(%esp), %eax
        cmpl $-2147483648, %eax
        sbbl $-1, %eax
        sarl $1, %eax
        negl %eax
        ret

llvm-svn: 16760
 2004-10-06 04:02:39 +00:00
Chris Lattner
acd213fba3 Add some new instructions. Fix the asm string for sbb32rr 
llvm-svn: 16759
 2004-10-06 04:01:02 +00:00
Chris Lattner
b2e8fdc431 FreeBSD uses GCC. Patch contributed by Jeff Cohen! 
llvm-svn: 16756
 2004-10-06 03:15:44 +00:00
Chris Lattner
0228f228df * Prune #includes 
* Update comments
* Rearrange code a bit
* Finally ELIMINATE the GAS workaround emitter for Intel mode.  woot!

llvm-svn: 16647
 2004-10-04 07:31:08 +00:00
Chris Lattner
581948c8f6 Add support for emitting AT&T style .s files, and make it the default. Users 
may now choose their output format with the -x86-asm-syntax={intel|att} flag.

llvm-svn: 16646
 2004-10-04 07:24:48 +00:00
Chris Lattner
5959f4a108 Convert some missed patterns to support AT&T style 
llvm-svn: 16645
 2004-10-04 07:23:07 +00:00
Chris Lattner
a05d9f53bb Apparently the GNU assembler has a HUGE hack to be compatible with really 
old and broken AT&T syntax assemblers.  The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.

llvm-svn: 16644
 2004-10-04 07:08:46 +00:00
Chris Lattner
08098895db Fix incorrect suffix 
llvm-svn: 16642
 2004-10-04 05:20:16 +00:00
Chris Lattner
c2fc9597bd Fix some more missed suffixes and swapped operands 
llvm-svn: 16641
 2004-10-04 01:38:10 +00:00
Chris Lattner
7b15a84728 Add missing suffixes to FP instructions for AT&T mode 
llvm-svn: 16640
 2004-10-04 00:43:31 +00:00
Chris Lattner
8d44dcca97 Add support for the -x86-asm-syntax flag, which can be used to choose between 
Intel and AT&T style assembly language.  The ultimate goal of this is to
eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission
is not fully operational.

llvm-svn: 16639
 2004-10-03 20:36:57 +00:00
Chris Lattner
94780713a8 Add support to the instruction patterns for AT&T style output, which will 
hopefully lead to the death of the 'GasBugWorkaroundEmitter'.  This also
includes changes to wrap the whole file to 80 columns! Woot! :)

Note that the AT&T style output has not been tested at all.

llvm-svn: 16638
 2004-10-03 20:35:00 +00:00
Chris Lattner
30b5b79aa0 Add initial support for variants 
llvm-svn: 16635
 2004-10-03 19:34:18 +00:00
Brian Gaeke
ee0dfdd1e1 Make EmitMappingInfo into an "external location" option, so that it can be set 
or cleared externally.

llvm-svn: 16623
 2004-09-30 20:20:01 +00:00
Brian Gaeke
c667e351ed I think this will handle double args. 
llvm-svn: 16618
 2004-09-30 19:44:32 +00:00
Brian Gaeke
0d4d060dbd Mark the instructions that have delay slots with the hasDelaySlot flag. 
Add some comments.

llvm-svn: 16611
 2004-09-30 04:04:48 +00:00
Brian Gaeke
738005408e Use TargetMachine::hasDelaySlot() instead of our old switch statement 
to find instrs that have delay slots.

llvm-svn: 16610
 2004-09-30 04:04:47 +00:00