RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity
37,195 Commits 4 Branches 5 Tags 704 MiB
f8b1257d2e
Commit Graph

29 Commits

Author SHA1 Message Date
Nicolas Geoffray
72fa78e195 Enable exception handling int JIT 
llvm-svn: 47079
 2008-02-13 18:39:37 +00:00
Chris Lattner
b067edf1b3 don't create the post-ra scheduler unless it is enabled. 
llvm-svn: 45972
 2008-01-14 19:00:06 +00:00
Gordon Henriksen
759ed9d805 Ammending r45669 with a missing file. 
llvm-svn: 45671
 2008-01-07 01:33:09 +00:00
Chris Lattner
9428a7d97f allow sinking to be enabled for the jit 
llvm-svn: 45624
 2008-01-05 06:14:16 +00:00
Bill Wendling
13eb1bfc08 Move option to enable machine LICM into LLVMTargetMachine.cpp. 
llvm-svn: 45572
 2008-01-04 08:11:03 +00:00
Chris Lattner
f4972fa569 Add a really quick hack at a machine code sinking pass, enabled with --enable-sinking. 
It is missing validity checks, so it is known broken.  However, it is powerful enough
to compile this contrived code:

void test1(int C, double A, double B, double *P) {
  double Tmp = A*A+B*B;
  *P = C ? Tmp : A;
}

into:

_test1:
	movsd	8(%esp), %xmm0
	cmpl	$0, 4(%esp)
	je	LBB1_2	# entry
LBB1_1:	# entry
	movsd	16(%esp), %xmm1
	mulsd	%xmm1, %xmm1
	mulsd	%xmm0, %xmm0
	addsd	%xmm1, %xmm0
LBB1_2:	# entry
	movl	24(%esp), %eax
	movsd	%xmm0, (%eax)
	ret

instead of:

_test1:
	movsd	16(%esp), %xmm0
	mulsd	%xmm0, %xmm0
	movsd	8(%esp), %xmm1
	movapd	%xmm1, %xmm2
	mulsd	%xmm2, %xmm2
	addsd	%xmm0, %xmm2
	cmpl	$0, 4(%esp)
	je	LBB1_2	# entry
LBB1_1:	# entry
	movapd	%xmm2, %xmm1
LBB1_2:	# entry
	movl	24(%esp), %eax
	movsd	%xmm1, (%eax)
	ret

woo.

llvm-svn: 45570
 2008-01-04 07:36:53 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Bill Wendling
c08dedb060 Initial commit of the machine code LICM pass. It successfully hoists this: 
_foo:
        li r2, 0
LBB1_1: ; bb
        li r5, 0
        stw r5, 0(r3)
        addi r2, r2, 1
        addi r3, r3, 4
        cmplw cr0, r2, r4
        bne cr0, LBB1_1 ; bb
LBB1_2: ; return
        blr 

to:

_foo:
        li r2, 0
        li r5, 0
LBB1_1: ; bb
        stw r5, 0(r3)
        addi r2, r2, 1
        addi r3, r3, 4
        cmplw cr0, r2, r4
        bne cr0, LBB1_1 ; bb
LBB1_2: ; return
        blr

ZOMG!! :-)

Moar to come...

llvm-svn: 44687
 2007-12-07 21:42:31 +00:00
Christopher Lamb
55a1e36013 Move subreg lowering pass to be right after regalloc, per feedback. 
llvm-svn: 40548
 2007-07-27 07:36:14 +00:00
Christopher Lamb
258dab5389 Add a MachineFunction pass, which runs post register allocation, that turns subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions. 
llvm-svn: 40521
 2007-07-26 08:18:32 +00:00
Evan Cheng
cdb4e7949f Added -print-emitted-asm to print out JIT generated asm to cerr. 
llvm-svn: 40123
 2007-07-20 21:56:13 +00:00
Dale Johannesen
1a9d304c35 Modify previous patch per review comments. 
llvm-svn: 39817
 2007-07-13 17:31:29 +00:00
Dale Johannesen
469ed8e17e Skeleton of post-RA scheduler; doesn't do anything yet. 
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816
 2007-07-13 17:13:54 +00:00
Duncan Sands
bfbe683782 Exception handling has been implemented. 
llvm-svn: 39732
 2007-07-11 16:59:20 +00:00
Chris Lattner
653c0ccfbe document and hide two options. 
llvm-svn: 37651
 2007-06-19 05:47:49 +00:00
Dale Johannesen
738f94210c name change requested by review of previous patch 
llvm-svn: 37289
 2007-05-22 18:31:04 +00:00
Dale Johannesen
fe0fe14411 Make tail merging the default, except on powerPC. There was no prior art 
for a target-dependent default with a command-line override; this way
should be generally usable.

llvm-svn: 37285
 2007-05-22 17:14:46 +00:00
Chris Lattner
f01b0a800b move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare". 
llvm-svn: 35529
 2007-03-31 04:18:03 +00:00
Chris Lattner
330464a91c Add a -print-lsr-output option to LLC, to print the output of the LSR pass. 
llvm-svn: 35522
 2007-03-31 00:24:43 +00:00
Devang Patel
0b82378a28 Now LoopStrengthReduce is a LoopPass. 
llvm-svn: 34984
 2007-03-06 21:14:09 +00:00
Jim Laskey
25993e18e6 Use exception flag. 
llvm-svn: 34496
 2007-02-22 16:22:15 +00:00
Bill Wendling
ccf772cc6b Split the addPassesToEmitFile method up into two. This is so that we can 
do some common stuff, then on our own add an object file writer (by calling
a concrete function), and then do some finishing stuff, if need be.

llvm-svn: 34032
 2007-02-08 01:36:53 +00:00
Bill Wendling
4d1444725b Removed more <iostream> includes 
llvm-svn: 32321
 2006-12-07 20:28:15 +00:00
Chris Lattner
0d40275b0e enable the branch folding pass for the JIT. 
llvm-svn: 31777
 2006-11-16 01:00:07 +00:00
Jim Laskey
7e0f0b2d24 1. Add a pass to fold debug label instructions so a debug info client can detect 
empty ranges.

2. Reorg how MachineDebugInfo maintains changes to debug labels.

3. Have dwarf writer use debug label info to simplify scopes and source line
coorespondence.

4. Revert the merging of compile units until I can get the bugs ironed out.

llvm-svn: 31507
 2006-11-07 19:33:46 +00:00
Jim Laskey
55d57252c3 Don't do dead block elimination in fast mode. 
llvm-svn: 31155
 2006-10-24 16:11:49 +00:00
Chris Lattner
87d16e0ed9 add the branch folding pass as a late cleanup pass for all targets. For now 
it just deletes empty MBB's.  Soon it will do more :)

llvm-svn: 30941
 2006-10-13 20:45:56 +00:00
Duraid Madina
51396ffd3e add setJumpBufSize() and setJumpBufAlignment() to target-lowering. 
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example

llvm-svn: 30095
 2006-09-04 06:21:35 +00:00
Chris Lattner
93ed29cb5d new file 
llvm-svn: 30082
 2006-09-04 04:16:09 +00:00