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Author SHA1 Message Date
Jim Grosbach
8681f76f38 Tidy up. No functional change. 
llvm-svn: 145843
 2011-12-05 20:09:44 +00:00
Jim Grosbach
7b62c2f71d ARM assmebler parsing for two-operand VMUL instructions. 
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

llvm-svn: 145842
 2011-12-05 19:55:46 +00:00
Anna Zaks
431b43fdbe Change the Dominators recalculate() function to only rely on GraphTraits 
This is a patch by Guoping Long!

As part of utilizing LLVM Dominator computation in Clang, made two changes to LLVM dominators tree implementation:

 - (1) Change the recalculate() template function to only rely on GraphTraits.
 - (2) Add a size() method to GraphTraits template class to query the number of nodes in the graph.

llvm-svn: 145837
 2011-12-05 19:17:04 +00:00
Hal Finkel
c8d6ce5e09 Add test case - this input used to crash because of duplicate generation of SPILL_CRs 
llvm-svn: 145820
 2011-12-05 17:55:22 +00:00
Hal Finkel
8b1e460cd9 enable PPC register scavenging by default (update tests and remove some FIXMEs) 
llvm-svn: 145819
 2011-12-05 17:55:17 +00:00
Hal Finkel
1a4a59ed2a don't include CR bit subregs in callee-saved list 
llvm-svn: 145818
 2011-12-05 17:55:12 +00:00
Hal Finkel
68e102ed41 remove wasted space for extra bit copies of CR2 subregs 
llvm-svn: 145817
 2011-12-05 17:55:06 +00:00
Hal Finkel
67924a349b add register pressure for CR regs 
llvm-svn: 145816
 2011-12-05 17:54:17 +00:00
Benjamin Kramer
f274d5feac Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small basic blocks. 
- Calling getUser in a loop is much more expensive than iterating over a few instructions.
- Use it instead of the open-coded loop in AddrModeMatcher.
- 5% speedup on ARMDisassembler.cpp Release builds.

llvm-svn: 145810
 2011-12-05 17:23:27 +00:00
NAKAMURA Takumi
c6a187dfdd test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux. 
llvm-svn: 145805
 2011-12-05 07:54:57 +00:00
Craig Topper
e873d61004 Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions. 
llvm-svn: 145804
 2011-12-05 07:27:14 +00:00
Craig Topper
02e1c33dca Clean up and optimizations to the X86 shuffle lowering code. No functional change. 
llvm-svn: 145803
 2011-12-05 06:56:46 +00:00
Nadav Rotem
1a91e4381d Add support for vectors of pointers. 
llvm-svn: 145801
 2011-12-05 06:29:09 +00:00
Jakub Staszak
2941ddc16d Fix table of contents. 
llvm-svn: 145793
 2011-12-04 20:44:25 +00:00
Jakub Staszak
01c388c624 Add 'llvm.expect' intrinsic description. 
llvm-svn: 145792
 2011-12-04 18:29:26 +00:00
Eric Christopher
5697266013 Add inline subprogram names to the name lookup table since they may 
not get there any other way.

llvm-svn: 145789
 2011-12-04 06:02:38 +00:00
Bob Wilson
f054e82281 Fix 80-column issues. 
llvm-svn: 145783
 2011-12-04 00:52:23 +00:00
Anton Korobeynikov
e2277de6a7 Emit the ctors in the proper order on ARM/EABI. 
Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!

llvm-svn: 145781
 2011-12-03 23:49:37 +00:00
Venkatraman Govindaraju
a942dee2b8 Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since 
AnalyzeBranch doesn't change the successor, just the order.

llvm-svn: 145779
 2011-12-03 21:24:48 +00:00
Benjamin Kramer
ab489e4c97 Simplify code. No functionality change. 
-3% on ARMDissasembler.cpp.

llvm-svn: 145773
 2011-12-03 16:18:22 +00:00
Benjamin Kramer
4ff0db784c Clear the new cache. 
llvm-svn: 145771
 2011-12-03 15:19:55 +00:00
Benjamin Kramer
ed1cd704e0 Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache just to remove no blocks from the maps. 
-15% on ARMDisassembler.cpp (Release build).  It's not that great to add another
layer of caching to the caching-heavy LVI but I don't see a better way.

llvm-svn: 145770
 2011-12-03 15:16:45 +00:00
Sanjoy Das
fe35e107cd Check for stack space more intelligently. 
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit.  This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit.  This should result in lesser calls to __morestack.

llvm-svn: 145766
 2011-12-03 09:32:07 +00:00
Sanjoy Das
d1c3d82afe Fix a bug in the x86-32 code generated for segmented stacks. 
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp.  This isn't correct since __morestack expects the call
to be followed directly by a ret.

This commit also adjusts the relevant test-case.

llvm-svn: 145765
 2011-12-03 09:21:07 +00:00
Nick Lewycky
2b2f028dcc Creating multiple JITs on X86 in multiple threads causes multiple writes (of 
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.

llvm-svn: 145745
 2011-12-03 02:45:50 +00:00
Chad Rosier
d1968c9ed6 [arm-fast-isel] Unaligned stores of floats require special care. 
rdar://10510150

llvm-svn: 145742
 2011-12-03 02:21:57 +00:00
Pete Cooper
32e376f7e1 Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur 
Turns out long long + unsigned long long is unsigned.  Doh!

Fixes http://llvm.org/bugs/show_bug.cgi?id=11455

llvm-svn: 145731
 2011-12-03 00:04:30 +00:00
Chad Rosier
d830d783e2 Add support for constant folding the pow intrinsic. 
rdar://10514247

llvm-svn: 145730
 2011-12-03 00:00:03 +00:00
Jim Grosbach
fb734dff3c ARM NEON VEXT aliases for data type suffices. 
llvm-svn: 145726
 2011-12-02 23:34:39 +00:00
Jim Grosbach
b15f862d86 ARM VEXT tighten up operand classes a bit. 
llvm-svn: 145722
 2011-12-02 22:57:57 +00:00
Jim Grosbach
3b245f9c39 ARM VST1 single lane assembly parsing. 
llvm-svn: 145718
 2011-12-02 22:34:51 +00:00
Akira Hatanaka
16d404cca1 Test cases for 64-bit multiplication and division. 
llvm-svn: 145717
 2011-12-02 22:31:36 +00:00
Akira Hatanaka
8a6af7933c Fix test cases to use FileCheck. 
llvm-svn: 145716
 2011-12-02 22:28:09 +00:00
Nick Lewycky
7d0d3c2d58 Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
 2011-12-02 22:16:29 +00:00
Jim Grosbach
6ae4df64e7 ARM tests for VLD1 single lane w/ writeback. 
llvm-svn: 145713
 2011-12-02 22:03:52 +00:00
Jim Grosbach
82ae7f46ea ARM VLD1 single lane assembly parsing. 
llvm-svn: 145712
 2011-12-02 22:01:52 +00:00
Jim Grosbach
cbde5d4877 ARM encoder method needs the physical register number, not the enum. 
llvm-svn: 145711
 2011-12-02 22:01:25 +00:00
Dylan Noblesmith
eb962ee28f TargetMachine: document unnamed bool argument 
Its meaning was slightly mysterious without looking at
subclasses.

llvm-svn: 145705
 2011-12-02 20:53:57 +00:00
Dylan Noblesmith
6978c891cf unittests: add ErrorStr to ExecutionEngine test 
Makes failures more self-explanatory.

llvm-svn: 145704
 2011-12-02 20:53:53 +00:00
Chad Rosier
b3b2871bbf [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

llvm-svn: 145701
 2011-12-02 20:25:18 +00:00
Hal Finkel
a5b78f0e58 specify cpu for test to fix failure on some darwin systems with a g4+ cpu 
llvm-svn: 145699
 2011-12-02 19:38:17 +00:00
Jim Grosbach
a568ef0db6 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
 2011-12-02 18:52:30 +00:00
Benjamin Kramer
c477861998 Fix quadratic behavior in InlineFunction by fetching the personality function of the callee once and not for every invoke in the caller. 
The callee is usually smaller than the caller, too. This reduces the compile
time of ARMDisassembler.cpp by 32% (Release build). It still takes ages to
compile though.

llvm-svn: 145690
 2011-12-02 18:37:31 +00:00
Jim Grosbach
129c6dbc32 Check for error after InstantiateMultclassDef. 
llvm-svn: 145689
 2011-12-02 18:33:03 +00:00
Jan Sjödin
81ee97461c Add XOP feature flag. 
llvm-svn: 145682
 2011-12-02 15:14:37 +00:00
Craig Topper
c67b7d7e2c Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions 
llvm-svn: 145681
 2011-12-02 08:18:41 +00:00
Craig Topper
d381116357 Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors. 
llvm-svn: 145680
 2011-12-02 07:16:01 +00:00
Hal Finkel
c90c9f608e remove unneeded FIXME comment 
llvm-svn: 145679
 2011-12-02 04:58:17 +00:00
Hal Finkel
2984a1dfcb adjust the instruction ordering in some PPC tests: changes due to postRA haz. rec. 
llvm-svn: 145678
 2011-12-02 04:58:12 +00:00
Hal Finkel
9ffa9b3c7f make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instruction in Sequence is a Noop 
llvm-svn: 145677
 2011-12-02 04:58:07 +00:00