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7188 Commits

Author SHA1 Message Date
Evan Cheng
fa864ab886 Add Thumb2 pkhbt / pkhtb. 
llvm-svn: 74895
 2009-07-07 05:35:52 +00:00
Evan Cheng
46b98516f6 Add some more Thumb2 multiplication instructions. 
llvm-svn: 74889
 2009-07-07 01:17:28 +00:00
Evan Cheng
5a279bb4b2 Add bfc to armv6t2. 
llvm-svn: 74868
 2009-07-06 22:23:46 +00:00
Evan Cheng
2570d8b541 Added ARM::mls for armv6t2. 
llvm-svn: 74866
 2009-07-06 22:05:45 +00:00
Evan Cheng
29ce3bfbb8 Avoid adding a duplicate def. This fixes PR4478. 
llvm-svn: 74857
 2009-07-06 21:34:05 +00:00
Stuart Hastings
7ab35df2d2 Mark this test as Darwin only. Patch by Bill Wendling. 
llvm-svn: 74829
 2009-07-06 15:36:23 +00:00
Nick Lewycky
d9573d899d When comparing constants, consider a less wide constant to be "less complex" 
than a wider one, before trying to compare their contents which will crash
if their sizes are different.

llvm-svn: 74792
 2009-07-04 17:24:52 +00:00
Evan Cheng
f20e4fba49 Add thumb2 sign / zero extend with rotate instructions. 
llvm-svn: 74755
 2009-07-03 01:43:10 +00:00
Evan Cheng
162bd9cead Added indexed stores. 
llvm-svn: 74740
 2009-07-03 00:06:39 +00:00
Evan Cheng
fcab8e743a Sign extending pre/post indexed loads. 
llvm-svn: 74736
 2009-07-02 23:16:11 +00:00
Chris Lattner
54c0359890 do not try to analyze bitcasts from i64 to <2 x i32> in ComputedMaskedBits. While 
we could do this, doing so requires adjusting the demanded mask and the code isn't 
doing that yet.  This fixes PR4495

llvm-svn: 74699
 2009-07-02 16:04:08 +00:00
Evan Cheng
dad6a41d14 Thumb2 pre/post indexed loads. 
llvm-svn: 74696
 2009-07-02 07:28:31 +00:00
Chris Lattner
4cddab0f14 @GOTPCREL is also rip-relative. Fix fast-isel to do the right thing. 
This fixes an llvm-gcc bootstrap problem I introduced.

llvm-svn: 74691
 2009-07-02 04:22:01 +00:00
Chris Lattner
e703feb0ac Fix yet-another bug I introduced into fastisel, this time handling 
constant pool references that weren't getting properly rip-relative.

llvm-svn: 74689
 2009-07-02 03:14:25 +00:00
Daniel Dunbar
298ac2d87c llvm-mc/x86: Test case for x86 operand parsing. 
llvm-svn: 74688
 2009-07-02 02:28:23 +00:00
Dan Gohman
e3b1f9e14b Fix an instcombine abort on a scalar-to-vector bitcast. This fixes PR4487. 
llvm-svn: 74646
 2009-07-01 21:38:46 +00:00
Devang Patel
86e8a3a0a8 new test case 
llvm-svn: 74633
 2009-07-01 19:40:59 +00:00
Devang Patel
905d32435c Support stand alone metadata syntax. 
!0 = constant metadata !{i32 21, i32 22}
@llvm.blah = constant metadata !{i32 1000, i16 200, metadata !0}

llvm-svn: 74630
 2009-07-01 19:21:12 +00:00
Chris Lattner
b51c7950bf Fix codegen for references to available_externally symbols. This fixes 
PR4482.

llvm-svn: 74613
 2009-07-01 16:53:44 +00:00
Stuart Hastings
4db03551ba Insure that __block_holder_tmp is allocated on the stack when a byref 
variable is present.

llvm-svn: 74610
 2009-07-01 15:40:10 +00:00
Evan Cheng
e6989735a6 CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp). 
llvm-svn: 74602
 2009-07-01 08:29:08 +00:00
Evan Cheng
7d78cb531e Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def. 
Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.

llvm-svn: 74601
 2009-07-01 08:19:36 +00:00
Chris Lattner
2bbdc61f92 Fix some fast-isel problems selecting global variable addressing in 
pic mode.

llvm-svn: 74582
 2009-07-01 03:27:19 +00:00
Evan Cheng
37503e9671 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. 
llvm-svn: 74580
 2009-07-01 01:59:31 +00:00
David Goodwin
19aa5c7d51 Add PIC load and store patterns for Thumb-2. 
llvm-svn: 74577
 2009-07-01 00:01:13 +00:00
Daniel Dunbar
d0589c59b3 llvm-mc: Symbols in a relocatable expression of the (a - b + cst) form are 
allowed to be undefined when the expression is seen, we cannot enforce the
same-section requirement until the entire assembly file has been seen.

llvm-svn: 74565
 2009-06-30 22:49:27 +00:00
David Goodwin
5805e9aef5 Add thumb-2 store word, halfword, and byte. 
llvm-svn: 74555
 2009-06-30 22:11:34 +00:00
David Goodwin
aad223dd8a Improve Thumb-2 jump table support. 
llvm-svn: 74549
 2009-06-30 19:50:22 +00:00
Rafael Espindola
340632e814 Fix PR4485. 
Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would
cause one register to remain on the stack at the function return.

llvm-svn: 74534
 2009-06-30 16:40:03 +00:00
Rafael Espindola
33b0aa0274 Fix PR4484. 
This was caused by me confounding FP0 and ST(0).

llvm-svn: 74523
 2009-06-30 12:18:16 +00:00
Evan Cheng
28b9e77f19 Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.). 
llvm-svn: 74519
 2009-06-30 09:19:42 +00:00
Evan Cheng
c6c942b70f Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. 
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518
 2009-06-30 08:49:04 +00:00
Evan Cheng
2a527c3419 A few more load instructions. 
llvm-svn: 74500
 2009-06-30 02:15:48 +00:00
Andreas Bolka
71ef361d1d Array accesses are independent if the underlying arrays differ. 
llvm-svn: 74499
 2009-06-30 02:12:10 +00:00
Daniel Dunbar
2d92d62fb2 llvm-mc: Accept relocatable expressions for .org, assignments, .byte, etc. 
llvm-svn: 74498
 2009-06-30 02:10:03 +00:00
David Goodwin
6ed9f9c9c5 Enhance tests to include shifted-register operand testing. 
llvm-svn: 74490
 2009-06-30 01:02:20 +00:00
Daniel Dunbar
e4fd18eda8 llvm-mc: Parse symbol attribute directives. 
llvm-svn: 74487
 2009-06-30 00:33:19 +00:00
Daniel Dunbar
72c0434597 llvm-mc: Parse .{,b,p2}align{,w,l} directives. 
llvm-svn: 74478
 2009-06-29 23:46:59 +00:00
David Goodwin
4f53387d26 Add Thumb-2 support for TEQ amd TST. 
llvm-svn: 74468
 2009-06-29 22:49:42 +00:00
David Goodwin
e7df96eedf Thumb-2 tests 
llvm-svn: 74464
 2009-06-29 22:25:22 +00:00
Daniel Dunbar
fca88cf26b llvm-mc: Recognize C++ style comments. 
llvm-svn: 74463
 2009-06-29 22:00:57 +00:00
Daniel Dunbar
ade4f03bd0 MC: Improve expression parsing and implement evaluation of absolute expressions. 
llvm-svn: 74448
 2009-06-29 20:37:27 +00:00
Dan Gohman
d496b35af0 Don't cache PHI exit values from exhaustive evaluations, because 
an individual exhaustive evaluation reflects only the exit value
implied by an individual exit, which may differ from the actual
exit value of the loop if there are other exits. This fixes PR4477.

llvm-svn: 74447
 2009-06-29 20:34:13 +00:00
Rafael Espindola
a0fdda93be FIX PR 4459. 
Not sure I understand how the temp register gets used,
but this fixes a bug and introduces no regressions.

llvm-svn: 74446
 2009-06-29 20:29:59 +00:00
David Greene
f39b82b3b3 Add some tests of advanced TableGen list functionality. 
llvm-svn: 74445
 2009-06-29 20:07:17 +00:00
David Goodwin
9e1280adf3 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. 
llvm-svn: 74423
 2009-06-29 15:33:01 +00:00
Evan Cheng
093adf3ff9 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
 2009-06-29 07:51:04 +00:00
Andreas Bolka
bed5622fb7 Print pairwise dependence results, add testcases. 
llvm-svn: 74402
 2009-06-28 00:35:22 +00:00
Dan Gohman
28702fab4e Don't try to split a loop when the controlling icmp instruction 
doesn't have an IV-based operand. This fixes PR4471.

llvm-svn: 74399
 2009-06-27 22:58:27 +00:00
Dan Gohman
8d2a45fadb Teach LoopSimplify how to merge multiple loop exits into a single exit, 
when one of them can be converted to a trivial icmp and conditional
branch.

This addresses what is essentially a phase ordering problem.
SimplifyCFG knows how to do this transformation, but it doesn't do so
if the primary block has any instructions in it other than an icmp and
a branch. In the given testcase, the block contains other instructions,
however they are loop-invariant and can be hoisted. SimplifyCFG doesn't
have LoopInfo though, so it can't hoist them. And, it's important that
the blocks be merged before LoopRotation, as it doesn't support
multiple-exit loops.

llvm-svn: 74396
 2009-06-27 21:30:38 +00:00