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Commit Graph

154508 Commits

Author SHA1 Message Date
Yonghong Song
fb1a6e5e60 bpf: initial 32-bit ALU encoding support in assembler
This patch adds instruction patterns for operations in BPF_ALU. After this,
assembler could recognize some 32-bit ALU statement. For example, those listed
int the unit test file.

Separate MOV patterns are unnecessary as MOV is ALU operation that could reuse
ALU encoding infrastructure, this patch removed those redundant patterns.

Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 313961
2017-09-22 04:36:36 +00:00
Yonghong Song
c00f228e84 bpf: add 32bit register set
Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 313960
2017-09-22 04:36:35 +00:00
Yonghong Song
b655bb5721 bpf: refactor inst patterns with better inheritance
Arithmetic and jump instructions, load and store instructions are sharing
the same 8-bit code field encoding,

A better instruction pattern implemention could be the following inheritance
relationships, and each layer only encoding those fields which start to
diverse from that layer. This avoids some redundant code.

  InstBPF -> TYPE_ALU_JMP -> ALU/JMP
  InstBPF -> TYPE_LD_ST -> Load/Store

Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 313959
2017-09-22 04:36:34 +00:00
Yonghong Song
e7fa849142 bpf: refactor inst patterns with more mnemonics
Currently, eBPF backend is using some constant directly in instruction patterns,
This patch replace them with mnemonics and removed some unnecessary temparary
variables.

Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 313958
2017-09-22 04:36:32 +00:00
Saleem Abdulrasool
d1a0918ad2 AArch64: support SwiftCC properly on AAPCS64
The previous SwiftCC support for AAPCS64 was partially correct.  It
setup swiftself parameters in the proper register but failed to setup
swifterror in the correct register.  This would break compilation of
swift code for non-Darwin AAPCS64 conforming environments.

llvm-svn: 313956
2017-09-22 04:31:44 +00:00
Sanjoy Das
e733e91370 Rename markAsErased to erase, as pointed out in a previous review; NFC
llvm-svn: 313951
2017-09-22 01:47:41 +00:00
NAKAMURA Takumi
08d972ebce HexagonVectorLoopCarriedReuse.cpp: Apply LLVM_ATTRIBUTE_UNUSED. [-Wunused-function]
llvm-svn: 313947
2017-09-22 01:01:33 +00:00
NAKAMURA Takumi
546de223aa Reformat.
llvm-svn: 313946
2017-09-22 01:01:31 +00:00
Richard Trieu
d0ffda4101 Fix unused variable warning.
Move function call into debug macro to suppress unused variable warning
in non-debug builds.

llvm-svn: 313942
2017-09-21 23:48:01 +00:00
Eugene Zelenko
d02286ecdf [CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 313941
2017-09-21 23:20:16 +00:00
Adrian Prantl
1a6ef90ed9 Fix a bug in a historic bitcode testcase.
llvm-svn: 313940
2017-09-21 23:14:55 +00:00
Adrian Prantl
89a6a62936 Fix a bug in a historic bitcode testcase. NFC.
llvm-svn: 313939
2017-09-21 23:14:52 +00:00
Rafael Espindola
f112256d3c Convert the archive writer to use Error.
This found one place in lld that was not checking the error.

llvm-svn: 313937
2017-09-21 23:13:36 +00:00
Pranav Bhandarkar
e00c8617dd [Hexagon] - Fix testcase for the HexagonVectorLoopCarriedReuse pass.
llvm-svn: 313936
2017-09-21 23:11:28 +00:00
Rafael Espindola
e117aeb67f Use raw_ostream in functions that don't need to seek. NFC.
llvm-svn: 313935
2017-09-21 23:06:23 +00:00
Rafael Espindola
d44f66dc70 Simplify the logic for truncating UID and GID. NFC.
llvm-svn: 313933
2017-09-21 23:00:55 +00:00
Rafael Espindola
8cabb93b47 Revert "Add a testfile that I missed in a previous commit that added HexagonVectorLoopCarriedReuse pass"
This reverts commit r313926.

It was failing in some bots.

llvm-svn: 313931
2017-09-21 22:57:43 +00:00
Zachary Turner
38d9180afe Resubmit "[lit] Refactor out some more common lit configuration code."
There were two issues, one Python 3 specific related to Unicode,
and another which is that the tool substitution for lld no longer
rejected matches where a / preceded the tool name.

llvm-svn: 313928
2017-09-21 22:16:40 +00:00
Pranav Bhandarkar
f67c033028 Add a testfile that I missed in a previous commit that
added HexagonVectorLoopCarriedReuse pass

llvm-svn: 313926
2017-09-21 21:52:24 +00:00
Pranav Bhandarkar
399d97fb12 Enable the reuse of values computed in a previous loop iteration.
This patch adds a pass that removes the computation of provably redundant
expressions that have been computed earlier in a previous iteration. It
relies on the use of PHIs to identify loop carried dependences.

This is scalar replacement for vector types.

llvm-svn: 313925
2017-09-21 21:48:23 +00:00
Zachary Turner
59fc9d7d39 Revert "[lit] Refactor out some more common lit configuration code."
This is breaking several bots.  I have enough information to
investigate, so I'm reverting to green until I get it figured
out.

llvm-svn: 313922
2017-09-21 21:45:45 +00:00
Kevin Enderby
63cb9b07be Fix a bug in llvm-objdump when disassembling using the wrong default CPU
in the second slice of a Mach-O universal file.

The code in llvm-objdump in in DisassembleMachO() was getting the default
CPU then incorrectly setting into the global variable used for the -mcpu option
if that was not set.  This caused a second call to DisassembleMachO() to use
the wrong default CPU when disassembling the next slice in a Mach-O universal
file.  And would result in bad disassembly and an error message about an
recognized processor for the target:

% llvm-objdump -d -m -arch all  fat.macho-armv7s-arm64 
fat.macho-armv7s-arm64 (architecture armv7s):
(__TEXT,__text) section
armv7:
       0:	60 47 	bx	r12
fat.macho-armv7s-arm64 (architecture arm64):
'cortex-a7' is not a recognized processor for this target (ignoring processor)
'cortex-a7' is not a recognized processor for this target (ignoring processor)
(__TEXT,__text) section
___multc3:
       0:		.long	0x1e620810

rdar://34439149

llvm-svn: 313921
2017-09-21 21:45:02 +00:00
Zachary Turner
ff689f377b [lit] Refactor out some more common lit configuration code.
debuginfo-tests has need to reuse a lot of common configuration
from clang and lld, and in general it seems like all of the
projects which are tightly coupled (e.g. lld, clang, llvm, lldb,
etc) can benefit from knowing about one other.  For example,
lldb needs to know various things about how to run clang in its
test suite.  Since there's a lot of common substitutions and
operations that need to be shared among projects, sinking this
up into LLVM makes sense.

In addition, this patch introduces a function add_tool_substitution
which handles all the dirty intricacies of matching tool names
which was previously copied around the various config files.  This
is now a simple straightforward interface which is hard to mess
up.

Differential Revision: https://reviews.llvm.org/D37944

llvm-svn: 313919
2017-09-21 21:27:31 +00:00
Zachary Turner
1e564b48a1 [lit] Actually do normalize the case of files in the config map.
This has gone back and forth, but it seems this is necessary
after all.  realpath is not sufficient because if you have a
file named 'C:\foo.txt', then both realpath('c:\foo.txt') and
realpath(C:\foo.txt') return the string that was passed to them
exactly as is, meaning the case of the drive-letter won't match.

The problem before was not that we were normalizing the case of
items going into the config map, but rather that we were
normalizing the case of something we needed to print.  The value
that is used to key on the config map should never be printed.

llvm-svn: 313918
2017-09-21 21:27:11 +00:00
Geoff Berry
a649dfc42e [AArch64] Fix bug in store of vector 0 DAGCombine.
Summary:
Avoid using XZR/WZR directly as operands to split stores of zero
vectors.  Doing so can lead to the XZR/WZR being used by an instruction
that doesn't allow it (e.g. add).

Fixes bug 34674.

Reviewers: t.p.northover, efriedma, MatzeB

Subscribers: aemerson, rengolin, javed.absar, mcrosier, eraman, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D38146

llvm-svn: 313916
2017-09-21 21:10:06 +00:00
Marek Sokolowski
a5b6a9fded [llvm-readobj] Fix big-endian byte swap in WindowsResourceDumper.
The previous version of dumper implemented UTF-16 byte swap incorrectly
on big-endian machines. This now gets fixed.

Thanks to Bill Seurer for testing the patch locally.

Differential Review: https://reviews.llvm.org/D38150

llvm-svn: 313912
2017-09-21 20:36:38 +00:00
Jonas Devlieghere
becf1e3bbf [dwarfdump] Add verbose output for .debug-line section
This patch adds dumping of line table instructions as well as the final
state at each specified pc value in verbose mode. This is essentially
the same as the default in Darwin's dwarfdump. Dumping the actual line
table opcodes can be particularly useful for something like debugging a
bad `.debug_line` section.

Differential revision: https://reviews.llvm.org/D37971

llvm-svn: 313910
2017-09-21 20:15:30 +00:00
Craig Topper
691299ee64 [DAGCombiner] Slightly simplify some code by using APInt::isMask() and countTrailingOnes instead of getting active bits and checking if all the bits below that make a mask.
At least for the 64-bit and less case, we should be able to determine if we even have a mask without counting any bits. This also removes the need to explicitly check for 0 active bits, isMask will return false for 0.

llvm-svn: 313908
2017-09-21 20:12:19 +00:00
Reid Kleckner
b408a0c51d Re-land r313825: "[IR] Add llvm.dbg.addr, a control-dependent version of llvm.dbg.declare"
The fix is to avoid invalidating our insertion point in
replaceDbgDeclare:
     Builder.insertDeclare(NewAddress, DIVar, DIExpr, Loc, InsertBefore);
+    if (DII == InsertBefore)
+      InsertBefore = &*std::next(InsertBefore->getIterator());
     DII->eraseFromParent();

I had to write a unit tests for this instead of a lit test because the
use list order matters in order to trigger the bug.

The reduced C test case for this was:
  void useit(int*);
  static inline void inlineme() {
    int x[2];
    useit(x);
  }
  void f() {
    inlineme();
    inlineme();
  }

llvm-svn: 313905
2017-09-21 19:52:03 +00:00
Bjorn Pettersson
97ae88f12f [SelectionDAG] Pick correct frame index in LowerArguments
Summary:
SelectionDAGISel::LowerArguments is associating arguments
with frame indices (FuncInfo->setArgumentFrameIndex). That
information is later on used by EmitFuncArgumentDbgValue to
create DBG_VALUE instructions that denotes that a variable
can be found on the stack.

I discovered that for our (big endian) out-of-tree target
the association created by SelectionDAGISel::LowerArguments
sometimes is wrong. I've seen this happen when a 64-bit value
is passed on the stack. The argument will occupy two stack
slots (frame index X, and frame index X+1). The fault is
that a call to setArgumentFrameIndex is associating the
64-bit argument with frame index X+1. The effect is that the
debug information (DBG_VALUE) will point at the least significant
part of the arguement on the stack. When printing the
argument in a debugger I will get the wrong value.

I managed to create a test case for PowerPC that seems to
show the same kind of problem.

The bugfix will look at the datalayout, taking endianness into
account when examining a BUILD_PAIR node, assuming that the
least significant part is in the first operand of the BUILD_PAIR.
For big endian targets we should use the frame index from
the second operand, as the most significant part will be stored
at the lower address (using the highest frame index).

Reviewers: bogner, rnk, hfinkel, sdardis, aprantl

Reviewed By: aprantl

Subscribers: nemanjai, aprantl, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D37740

llvm-svn: 313901
2017-09-21 18:52:08 +00:00
Adrian Prantl
520bbabe3d llvm-dwarfdump support --debug-frame=<offset> and --eh-frame=<offset>
llvm-svn: 313900
2017-09-21 18:52:03 +00:00
Artem Belevich
93d70564c9 [NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} instructions/intrinsics/builtins.
Differential Revision: https://reviews.llvm.org/D38148

llvm-svn: 313898
2017-09-21 18:44:49 +00:00
Rafael Espindola
999461a0e4 Use ArrayRef. NFC.
llvm-svn: 313895
2017-09-21 17:51:07 +00:00
Sanjay Patel
ce603e3652 [x86] add more tests for node-level FMF; NFC
llvm-svn: 313893
2017-09-21 17:40:58 +00:00
Craig Topper
e1e5dec41c [DAGCombiner] Remove duplicate code from visitZERO_EXTEND
This exact block of code exists right below.

Differential Revision: https://reviews.llvm.org/D38122

llvm-svn: 313891
2017-09-21 17:30:02 +00:00
Zaara Syeda
95ca10d245 Fix buildbot failures, add mtriple to gpr-vsr-spill.ll
llvm-svn: 313890
2017-09-21 17:05:47 +00:00
Zachary Turner
53734be6a4 [lit] Don't norm case when inserting into the config map.
This makes all paths lowercase on Windows, which seemed like a
good idea at the time, but it means that tests can't properly
use FileCheck to match expected path names.

llvm-svn: 313889
2017-09-21 17:02:08 +00:00
Adrian Prantl
4055863a09 llvm-dwarfdump: Add support for the --arch command line option.
llvm-svn: 313888
2017-09-21 16:26:18 +00:00
Zachary Turner
93cdde161f [lit] Add a test for the builtin config map.
Config map is not exposed through the command line, so testing this
is somewhat tricky.  But basically we need a test that if a custom
driver builds a config map and passes it to main, it gets respected.

A config map allows config files in the source tree to be mapped
to alternate config files in the build tree.  This particular test
works by having two config files in separate directories, and
setting up a config map to have that redirects A/lit.site.cfg
to B/altconfig.  Then, we print a message in A/lit.site.cfg
and B/altconfig and check that we do see the output from B
but don't see the output from A.  Additionally we test that
the test suite specified by A's config map is properly discovered.

Differential Revision: https://reviews.llvm.org/D38105

llvm-svn: 313887
2017-09-21 16:18:28 +00:00
Zaara Syeda
465ce59a0d [Power9] Spill gprs to vector registers rather than stack
This patch updates register allocation to enable spilling gprs to
volatile vector registers rather than the stack. It can be enabled
 for Power9 with option -ppc-enable-gpr-to-vsr-spills.

Differential Revision: https://reviews.llvm.org/D34815

llvm-svn: 313886
2017-09-21 16:12:33 +00:00
Benjamin Kramer
c90e12840a Add missing file from r313884.
llvm-svn: 313885
2017-09-21 15:32:05 +00:00
Benjamin Kramer
58b0a1afcd [DWARF] Shrink AttributeSpec from 24 to 16 bytes.
This is a bit ugly because we can't put Optional into a union. Hide all
of that behind a set of accessors and make accesses safer using asserts.

llvm-svn: 313884
2017-09-21 15:27:45 +00:00
Simon Pilgrim
2f2ce511ad [X86][SSE] Add PSHUFLW/PSHUFHW tests inspired by PR34686
llvm-svn: 313883
2017-09-21 15:11:51 +00:00
Simon Atanasyan
0810cf52bd [mips] Implement generation of relocations "chains" used by N32 ABI
In case of using a "nested" relocation expressions like this
`%hi(%neg(%gp_rel()))`, N32 ABI requires generation of three consecutive
relocations. That differs from the N64 ABI case where all relocations
are packed into the single relocation record.

llvm-svn: 313879
2017-09-21 14:04:53 +00:00
Simon Atanasyan
7b4099eccc [mips] Do not pass redundant IsN64 flag to MCELFObjectTargetWriter. NFC
Now we pass the 'Is64_' flag to the MCELFObjectTargetWriter ctor iif
when we make deal with N64 ABI. So it is redundant to pass additional
'IsN64' flag.

llvm-svn: 313878
2017-09-21 14:04:47 +00:00
Jonas Paulsson
97ce9363d0 [SystemZ] Improve optimizeCompareZero()
More conversions to load-and-test can be made with this patch by adding a
forward search in optimizeCompareZero().

Review: Ulrich Weigand
https://reviews.llvm.org/D38076

llvm-svn: 313877
2017-09-21 13:52:24 +00:00
Daniel Jasper
9eea6fd83b Revert r313825: "[IR] Add llvm.dbg.addr, a control-dependent version of llvm.dbg.declare"
.. as well as the two subsequent changes r313826 and r313875.

This leads to segfaults in combination with ASAN. Will forward repro
instructions to the original author (rnk).

llvm-svn: 313876
2017-09-21 12:07:33 +00:00
Mikael Holmen
2e96ed2e60 [SROA] Really remove associated dbg.declare when removing dead alloca
Summary:
There already was code that tried to remove the dbg.declare, but that code
was placed after we had called
 I->replaceAllUsesWith(UndefValue::get(I->getType()));
on the alloca, so when we searched for the relevant dbg.declare, we
couldn't find it.

Now we do the search before we call RAUW so there is a chance to find it.

An existing testcase needed update due to this. Two dbg.declare with undef
were removed and then suddenly one of the two CHECKS failed.

Before this patch we got

  call void @llvm.dbg.declare(metadata i24* undef, metadata !14, metadata !DIExpression(DW_OP_LLVM_fragment, 32, 24)), !dbg !15
  call void @llvm.dbg.declare(metadata %struct.prog_src_register* undef, metadata !14, metadata !DIExpression()), !dbg !15
  call void @llvm.dbg.value(metadata i32 0, metadata !14, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 32)), !dbg !15
  call void @llvm.dbg.value(metadata i32 0, metadata !14, metadata !DIExpression(DW_OP_LLVM_fragment, 32, 24)), !dbg !15

and with it we get

  call void @llvm.dbg.value(metadata i32 0, metadata !14, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 32)), !dbg !15
  call void @llvm.dbg.value(metadata i32 0, metadata !14, metadata !DIExpression(DW_OP_LLVM_fragment, 32, 24)), !dbg !15

However, the CHECKs in the testcase checked things in a silly order, so
they only passed since they found things in the first dbg.declare. Now
we changed the order of the checks and the test passes.

Reviewers: rnk

Reviewed By: rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37900

llvm-svn: 313875
2017-09-21 11:14:27 +00:00
Javed Absar
5ddf70786d [TableGen] Tidy up CodeGenRegisters
Replacing range loops.

Reviewed by: @MatzeB
Differential Revision: https://reviews.llvm.org/D38091

llvm-svn: 313874
2017-09-21 10:51:47 +00:00
Simon Atanasyan
4ec35c8c3c [mips] Fix relocation record format and ELF header for N32 ABI
The N32 ABI uses RELA relocation format, do not use 3-in-1 relocation's
encoding, and uses ELFCLASS32. This change passes the `IsN32` flag
to the `MCAsmBackend` to distinguish usage of N32 ABI.

We still do not handle some cases like providing the `-target-abi=o32`
command line option with the `mips64` target triple. That's why
elf_header.s contains some "FIXME" strings. This case will be fixed in
a separate patch.

Differential revision: https://reviews.llvm.org/D37960

llvm-svn: 313873
2017-09-21 10:44:26 +00:00