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Commit Graph

238 Commits

Author SHA1 Message Date
Evan Cheng
cf13e0c732 Do not use frame register to reference fixed stack objects if the function is frameless. 
llvm-svn: 79067
 2009-08-15 02:05:35 +00:00
Evan Cheng
4e97ccc132 Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim. 
llvm-svn: 79039
 2009-08-14 20:48:13 +00:00
Owen Anderson
9df206d02d Push LLVMContexts through the IntegerType APIs. 
llvm-svn: 78948
 2009-08-13 21:58:54 +00:00
Jim Grosbach
3c898a99bd Whitespace cleanup. Remove trailing whitespace. 
llvm-svn: 78666
 2009-08-11 15:33:49 +00:00
Evan Cheng
f54e50e4e8 Use tMOVgpr2gpr instead of t2MOVr. 
llvm-svn: 78556
 2009-08-10 05:49:43 +00:00
Evan Cheng
48b49cf5b9 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
 2009-08-07 00:34:42 +00:00
Evan Cheng
c9f31ae969 When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. 
llvm-svn: 77642
 2009-07-30 23:29:25 +00:00
Chris Lattner
18af1b233a Give getPointerRegClass() a "kind" value so that targets can 
support multiple different pointer register classes.

llvm-svn: 77501
 2009-07-29 20:31:52 +00:00
Chris Lattner
8972d46576 more simplifications and cleanup. :) 
llvm-svn: 77350
 2009-07-28 18:48:43 +00:00
Evan Cheng
93c1b56fe9 Code clean up. No functionality changes. 
llvm-svn: 77301
 2009-07-28 06:24:12 +00:00
Evan Cheng
b740190d2e - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
Evan Cheng
fa630cca3f Get rid of more dead code. 
llvm-svn: 77227
 2009-07-27 18:38:54 +00:00
Evan Cheng
55e369a447 Cosmetic change. 
llvm-svn: 77222
 2009-07-27 18:31:40 +00:00
Evan Cheng
a773ae7a39 Get rid of some more getOpcode calls. 
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.

llvm-svn: 77218
 2009-07-27 18:20:05 +00:00
Evan Cheng
674c4d47b9 Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. 
llvm-svn: 77181
 2009-07-27 03:14:20 +00:00
Evan Cheng
d555fec28c Refactor. Get rid of a few more getOpcode() calls. 
llvm-svn: 77164
 2009-07-26 18:55:14 +00:00
Evan Cheng
0f605005c5 80 col violation. 
llvm-svn: 77041
 2009-07-25 01:55:25 +00:00
Owen Anderson
cc33e89571 Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come. 
llvm-svn: 77011
 2009-07-24 23:12:02 +00:00
Evan Cheng
d13b8f8353 FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets. 
llvm-svn: 76925
 2009-07-24 00:53:56 +00:00
David Goodwin
85bcdffa4f Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. 
llvm-svn: 76919
 2009-07-24 00:16:18 +00:00
David Goodwin
f3c839e0b9 Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. 
llvm-svn: 76883
 2009-07-23 17:06:46 +00:00
Evan Cheng
c21e149091 80 col violation. 
llvm-svn: 76872
 2009-07-23 07:58:08 +00:00
Evan Cheng
005330f8a0 Get rid one of the getRegisterNumbering. Also add D16 - D31. 
llvm-svn: 76725
 2009-07-22 05:55:18 +00:00
Owen Anderson
cc287b28c9 Get rid of the Pass+Context magic. 
llvm-svn: 76702
 2009-07-22 00:24:57 +00:00
Evan Cheng
7a6b20df7f Let callers decide the sub-register index on the def operand of rematerialized instructions. 
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900
 2009-07-16 09:20:10 +00:00
Owen Anderson
8c85061ee6 Move EVER MORE stuff over to LLVMContext. 
llvm-svn: 75703
 2009-07-14 23:09:55 +00:00
Torok Edwin
f955a6ef49 llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
 2009-07-14 16:55:14 +00:00
David Goodwin
9634e3ff8f Fix FP elimination code to work for Thumb-2 addrmode AddrModeT2_so. This fixes SingleSource/Benchmarks/Stanford/Queens (among others). 
llvm-svn: 75513
 2009-07-13 21:43:08 +00:00
Torok Edwin
ae8a3ff177 assert(0) -> LLVM_UNREACHABLE. 
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379
 2009-07-11 20:10:48 +00:00
Evan Cheng
268b47b1fb Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. 
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.

llvm-svn: 75359
 2009-07-11 06:43:01 +00:00
David Goodwin
6c4201dbcb Handle Thumb-2 addressing modes during FP elimination. 
llvm-svn: 75158
 2009-07-09 18:35:52 +00:00
David Goodwin
49fbd8d6b7 Use common code for both ARM and Thumb-2 instruction and register info. 
llvm-svn: 75067
 2009-07-08 23:10:31 +00:00
Evan Cheng
ef49d9c75b Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. 
llvm-svn: 75048
 2009-07-08 21:03:57 +00:00
Torok Edwin
358888da3a Implement changes from Chris's feedback. 
Finish converting lib/Target.

llvm-svn: 75043
 2009-07-08 20:53:28 +00:00
David Goodwin
94209a4c31 Generalize opcode selection in ARMBaseRegisterInfo. 
llvm-svn: 75036
 2009-07-08 20:28:28 +00:00
David Goodwin
c571c4b457 Push methods into base class in preparation for sharing. 
llvm-svn: 75020
 2009-07-08 18:31:39 +00:00
Torok Edwin
ad3be984b7 Start converting to new error handling API. 
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)

llvm-svn: 75018
 2009-07-08 18:01:40 +00:00
David Goodwin
7b4570ee1d Start breaking out common base functionality for register info. 
llvm-svn: 75016
 2009-07-08 17:28:55 +00:00