RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 12:02:58 +02:00
Code Issues Projects Releases Wiki Activity
67,157 Commits 4 Branches 5 Tags 704 MiB
fd0bab72a7
Commit Graph

205 Commits

Author SHA1 Message Date
Jim Grosbach
fd0bab72a7 ARMPseudoInst instructions should default to being considered a single 4-byte 
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274

llvm-svn: 119713
 2010-11-18 18:01:40 +00:00
Jim Grosbach
2f9a2efb3c ARM PseudoInst instructions don't need or use an assembler string. Get rid of 
the operand to the pattern.

llvm-svn: 119607
 2010-11-18 01:38:26 +00:00
Jim Grosbach
205e0345c1 Add FIXME. 
llvm-svn: 119603
 2010-11-18 01:20:48 +00:00
Jim Grosbach
a42e2b0fcb Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not 
just pretend to be.

llvm-svn: 119602
 2010-11-18 01:15:56 +00:00
Jim Grosbach
42d103250b Refactor a few ARM load instructions to better parameterize things and re-use 
common encoding information.

llvm-svn: 119598
 2010-11-18 00:46:58 +00:00
Jim Grosbach
b640b6a7b4 More ARM encoding bits. LDRH now encodes properly. 
llvm-svn: 119529
 2010-11-17 18:11:11 +00:00
Bill Wendling
0b16ba97fd Add binary emission stuff for VLDM/VSTM. This reuses the 
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.

llvm-svn: 119435
 2010-11-17 00:45:23 +00:00
Bill Wendling
2ac47f0959 - Remove dead patterns. 
- Add encodings to the *LDMIA_RET instrs. Probably not needed...

llvm-svn: 119323
 2010-11-16 02:08:45 +00:00
Jim Grosbach
7aabb8c5ee ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding. 
llvm-svn: 119180
 2010-11-15 20:47:07 +00:00
Chris Lattner
b2daeac125 add fields to the .td files unconditionally, simplifying tblgen a bit. 
Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120
 2010-11-15 05:19:05 +00:00
Bill Wendling
aa9ca6fcca Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the 
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.

llvm-svn: 118995
 2010-11-13 09:09:38 +00:00
Jim Grosbach
03eb1993ea More ARM load/store indexed refactoring. Also fix an incorrect IndexMode 
flag for the LDRT/STRT family instructions as a side effect.

llvm-svn: 118955
 2010-11-13 00:35:48 +00:00
Jim Grosbach
eaaf8294a5 Refactor to parameterize some ARM load/store encoding patterns. Preparatory 
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.

llvm-svn: 118925
 2010-11-12 21:28:15 +00:00
Evan Cheng
b565d1acf9 Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. 
llvm-svn: 118922
 2010-11-12 20:32:20 +00:00
Jim Grosbach
160cc37f73 Kill more unused stuff. 
llvm-svn: 118921
 2010-11-12 19:27:45 +00:00
Jim Grosbach
8bb507dd6b Remove unused class. 
llvm-svn: 118919
 2010-11-12 19:24:53 +00:00
Jim Grosbach
cbab1ea04e Encoding for ARM LDRSB instructions. 
llvm-svn: 118905
 2010-11-12 17:52:59 +00:00
Owen Anderson
85cf1b8ff5 Fill out support for Thumb2 encodings of NEON instructions. 
llvm-svn: 118854
 2010-11-11 23:12:55 +00:00
Owen Anderson
0913dac245 Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. 
llvm-svn: 118843
 2010-11-11 21:36:43 +00:00
Owen Anderson
f43f09f6f6 Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. 
More tests to come.

llvm-svn: 118819
 2010-11-11 19:07:48 +00:00
Jim Grosbach
cfc32e3b5a Encoding for ARM LDRSH_POST. 
llvm-svn: 118794
 2010-11-11 16:55:29 +00:00
Jim Grosbach
8cb10f8def Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names. 
llvm-svn: 118767
 2010-11-11 01:55:59 +00:00
Jim Grosbach
3b13f9013c ARM STRH encoding information. 
llvm-svn: 118757
 2010-11-11 01:09:40 +00:00
Jim Grosbach
2c1d6373ab Move LDM predicate operand encoding into base clase. Add STM missing STM 
encoding bits.

llvm-svn: 118738
 2010-11-10 23:44:32 +00:00
Jim Grosbach
ad037e5ded ARM LDM encoding for the mode (ia, ib, da, db) operand. 
llvm-svn: 118736
 2010-11-10 23:38:36 +00:00
Jim Grosbach
ef95eee920 Fix ARM encoding of non-return LDM instructions. 
llvm-svn: 118732
 2010-11-10 23:18:49 +00:00
Jim Grosbach
d832c84199 Fix ARM encoding of LDM+Return instruction. 
llvm-svn: 118730
 2010-11-10 23:12:48 +00:00
Bill Wendling
990c247994 Add encoding for VSTR. 
llvm-svn: 118220
 2010-11-04 00:59:42 +00:00
Owen Anderson
f754738bbb Revert r118097 to fix buildbots. 
llvm-svn: 118121
 2010-11-02 23:47:29 +00:00
Owen Anderson
ea89766d0c Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning. 
llvm-svn: 118097
 2010-11-02 22:41:42 +00:00
Owen Anderson
b34a5f1d02 Factor out a common encoding class for loads and stores with a lane parameter. 
llvm-svn: 118055
 2010-11-02 20:47:39 +00:00
Owen Anderson
6647eb222b Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Bill Wendling
69e7c09c32 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Jim Grosbach
53d2661c60 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Bill Wendling
da3d0ce7b5 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00
Chris Lattner
a4c36d0efe fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Jim Grosbach
996d1280bd Encode the register list operands for ARM mode LDM/STM instructions. 
llvm-svn: 117753
 2010-10-30 00:37:59 +00:00
Jim Grosbach
4ca61d9877 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS. 
llvm-svn: 117702
 2010-10-29 20:21:36 +00:00
Jim Grosbach
162e3345fb ARM mode LDREX*/STREX* binary encodings. 
llvm-svn: 117695
 2010-10-29 19:58:57 +00:00
Jim Grosbach
86ecfda983 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Owen Anderson
d28d229ded Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Owen Anderson
7c46fcfee4 Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Jim Grosbach
30f6744f05 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Owen Anderson
0cecbd810e Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Owen Anderson
b7618a821f Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00
Evan Cheng
59acb7e4cf NEON vmov's are in Neon domain. 
llvm-svn: 117347
 2010-10-26 02:03:05 +00:00
Owen Anderson
59e85cbd66 Add correct instruction encodings for vbic, vorn, and vmvn. 
llvm-svn: 117282
 2010-10-25 18:43:52 +00:00
Owen Anderson
2824342fac Provide correct NEON encodings for vand, veor, and vorr. 
llvm-svn: 117279
 2010-10-25 18:28:30 +00:00
Jim Grosbach
bba77cca02 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
llvm-svn: 117165
 2010-10-22 22:12:16 +00:00
Jim Grosbach
ca2897a0ca More ARM multiply instuction binary encodings. 
llvm-svn: 117121
 2010-10-22 18:35:16 +00:00