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37 Commits

Author SHA1 Message Date
Dan Gohman
5dad0993a9 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
llvm-svn: 60487
 2008-12-03 18:15:48 +00:00
Andrew Lenharth
c178981b85 llvm.memory.barrier, and impl for x86 and alpha 
llvm-svn: 47204
 2008-02-16 01:24:58 +00:00
Chris Lattner
14310afe42 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner
8b4b75c771 Change the 'isStore' inferrer to look for 'SDNPMayStore' 
instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654
 2008-01-06 06:44:58 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng
53cb03b583 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Andrew Lenharth
c894d4e3ce Use this nifty Constraints thing and fix the inverted conditional moves 
llvm-svn: 36191
 2007-04-17 04:07:59 +00:00
Andrew Lenharth
c4f8836525 Add all that branch mangling niftiness 
llvm-svn: 31313
 2006-10-31 16:49:55 +00:00
Andrew Lenharth
fe127f3de7 Let the alpha breakage begin. First Formals and RET. next Calls 
llvm-svn: 28753
 2006-06-12 18:09:24 +00:00
Andrew Lenharth
25de2846c5 Alpha Scheduling classes 
llvm-svn: 26643
 2006-03-09 17:16:45 +00:00
Andrew Lenharth
9812806d03 Add immediate forms of cmov and remove some cruft 
llvm-svn: 25882
 2006-02-01 19:37:33 +00:00
Andrew Lenharth
23afe2f288 minor renaming 
llvm-svn: 25640
 2006-01-26 03:24:15 +00:00
Andrew Lenharth
ad88ba7c98 allow R28 to be used for frame calculations without entirely removing it from circulation 
llvm-svn: 25639
 2006-01-26 03:22:07 +00:00
Andrew Lenharth
87cf023175 stack and rpcc 
llvm-svn: 25369
 2006-01-16 21:22:38 +00:00
Andrew Lenharth
33a683c939 Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel. 
llvm-svn: 25057
 2006-01-01 22:16:14 +00:00
Andrew Lenharth
f8a6d19367 add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG 
llvm-svn: 25011
 2005-12-25 17:36:48 +00:00
Andrew Lenharth
588bd3f659 Unify the patterns for loads and stores. Now offset addressing should be 
supported.  This almost completes memory operations.

llvm-svn: 25002
 2005-12-24 07:34:33 +00:00
Andrew Lenharth
5ce2a6c2cf move loads and stores over. Smart addr selection comming 
llvm-svn: 25000
 2005-12-24 03:41:56 +00:00
Andrew Lenharth
b294ecae1b OK, this does wonders for broken stuff 
llvm-svn: 24624
 2005-12-06 20:40:34 +00:00
Andrew Lenharth
b86d70f50a added instructions with inverted immediates 
llvm-svn: 24614
 2005-12-06 00:33:53 +00:00
Andrew Lenharth
0fdfe40762 These never trigger, but whatever 
llvm-svn: 24612
 2005-12-05 23:19:44 +00:00
Andrew Lenharth
dd3477b285 All sorts of stuff. 
Getting in on the custom lowering thing, yay
evilness with fp setcc, yuck
trivial int select, hmmm
in memory args for functions, yay
DIV and REM, always handy.  They should be custom lowered though.

Lots more stuff compiles now (go go single source!).  Of course, none of it
probably works, but that is what the nightly tester can find out :)

llvm-svn: 24533
 2005-11-30 07:19:56 +00:00
Andrew Lenharth
33e8022557 massive DAGISel patch. lots and lots more stuff compiles now 
llvm-svn: 24483
 2005-11-22 04:20:06 +00:00
Andrew Lenharth
dca2f13e76 continued readcyclecounter support 
llvm-svn: 24300
 2005-11-11 16:47:30 +00:00
Andrew Lenharth
1acb71df32 whatever. Intermediate patch to see what breaks. Seems ok. 
llvm-svn: 24260
 2005-11-09 19:17:08 +00:00
Andrew Lenharth
de7df19b83 Simplify instinfo, set random bits on more fp insts, and fix 1 opcode 
llvm-svn: 24014
 2005-10-26 17:41:46 +00:00
Andrew Lenharth
4d5b664423 Well, the Constant matching pattern works. Can't say much about calls or globals yet. 
llvm-svn: 23884
 2005-10-22 22:06:58 +00:00
Andrew Lenharth
065fe477eb Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expect new stuff to pass in the JIT tonight 
llvm-svn: 23852
 2005-10-20 23:58:36 +00:00
Andrew Lenharth
0856abb644 added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh 
llvm-svn: 23849
 2005-10-20 19:39:24 +00:00
Andrew Lenharth
a7554852b3 ret 0; works, not much else 
still lots of uglyness.
Maybe calls will come soon.
Fixing the return value of things will be necessary to make alpha work.

llvm-svn: 23832
 2005-10-20 00:28:31 +00:00
Andrew Lenharth
0fcc129f80 support bsr, and more .td simplification 
llvm-svn: 22543
 2005-07-28 18:14:47 +00:00
Andrew Lenharth
653f21b2cd simpilfy instruction encoding (and make the lines way shorter, aka Misha happification) 
llvm-svn: 22499
 2005-07-22 20:50:29 +00:00
Misha Brukman
75da90f127 Make the rest of file header comments consistent in format and style 
llvm-svn: 20048
 2005-02-05 02:24:26 +00:00
Andrew Lenharth
1f0b710fb6 initial fp support 
llvm-svn: 19847
 2005-01-26 21:54:09 +00:00
Andrew Lenharth
3b44cfa26d Clean ups, and taught the instruction selector about immediate forms 
llvm-svn: 19816
 2005-01-24 19:44:07 +00:00
Andrew Lenharth
f5b9a8fe57 Let me introduce you to the early stages of the llvm backend for the alpha processor 
llvm-svn: 19764
 2005-01-22 23:41:55 +00:00