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150980 Commits

Author SHA1 Message Date
Max Kazantsev
80de7d0d4d [IRCE][NFC] Better get SCEV for 1 in calculateSubRanges
A slightly more efficient way to get constant, we avoid resolving in getSCEV and excessive
invocations, and we don't create a ConstantInt if 'true' branch is taken.

Differential Revision: https://reviews.llvm.org/D34672

llvm-svn: 306503
2017-06-28 04:57:45 +00:00
Nirav Dave
c2c9b865bc Revert "[DAG] Fold FrameIndex offset into BaseIndexOffset analysis. NFCI."
This reverts commit r306498 which appears to cause a compilrt-rt test failures

llvm-svn: 306501
2017-06-28 03:20:04 +00:00
Stanislav Mekhanoshin
e33a7ff5b3 [AMDGPU] Add pattern for v_alignbit_b32 with immediate
If immediate in shift is less than 32 we can use alignbit too.

Differential Revision: https://reviews.llvm.org/D34729

llvm-svn: 306500
2017-06-28 02:52:39 +00:00
Stanislav Mekhanoshin
d6f4dc77a6 Allow to truncate left shift with non-constant shift amount
That is pretty common for clang to produce code like
(shl %x, (and %amt, 31)). In this situation we can still perform
trunc (shl) into shl (trunc) conversion given the known value
range of shift amount.

Differential Revision: https://reviews.llvm.org/D34723

llvm-svn: 306499
2017-06-28 02:37:11 +00:00
Nirav Dave
48ea968c3a [DAG] Fold FrameIndex offset into BaseIndexOffset analysis. NFCI.
Pull FrameIndex comparision reasoning from DAGCombiner::isAlias to
general BaseIndexOffset.

llvm-svn: 306498
2017-06-28 02:09:50 +00:00
Kyle Butt
d26e9cac39 Inlining: Don't re-map simplified cloned instructions.
When simplifying an instruction that has been re-mapped, it should never
simplify to an instruction in the original function. In the edge case
where we are inlining a function into itself, the existing code led to
incorrect behavior. Replace the incorrect code with an assert verifying
that we never expect simplification to produce an instruction in the old
function, unless the functions are the same.

Differential Revision: https://reviews.llvm.org/D33850

llvm-svn: 306495
2017-06-28 01:41:25 +00:00
Joel Jones
7714ff8dab [TableGen] Improve Debug Output for --debug-only=subtarget-emitter NFCI
Add headers for each section of output, with white space and "+++" to
improve readability.

Differential Revision: https://reviews.llvm.org/D34713

llvm-svn: 306492
2017-06-28 00:06:40 +00:00
Peter Collingbourne
17b70c2151 Add missing library dependency.
llvm-svn: 306491
2017-06-28 00:05:27 +00:00
Mandeep Singh Grang
1db9a50c96 [COFF, ARM64] Add support for Windows ARM64 COFF format
Summary:
This is the llvm part of the initial implementation to support Windows ARM64 COFF format.
I will gradually add more functionality in subsequent patches.

Reviewers: ruiu, rnk, t.p.northover, compnerd

Reviewed By: ruiu, compnerd

Subscribers: aemerson, mgorny, javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D34705

llvm-svn: 306490
2017-06-27 23:58:19 +00:00
Peter Collingbourne
8c0398b976 Object: Teach irsymtab::read() to try to use the irsymtab that we wrote to disk.
Fixes PR27551.

Differential Revision: https://reviews.llvm.org/D33974

llvm-svn: 306488
2017-06-27 23:50:24 +00:00
Peter Collingbourne
aaf2889bcd Bitcode: Write the irsymtab to disk.
Differential Revision: https://reviews.llvm.org/D33973

llvm-svn: 306487
2017-06-27 23:50:11 +00:00
Peter Collingbourne
03ec7b338f Object: Add version and producer fields to the irsymtab header. NFCI.
These will be necessary in order to handle upgrades from old bitcode
files.

Differential Revision: https://reviews.llvm.org/D33972

llvm-svn: 306486
2017-06-27 23:49:58 +00:00
Sanjay Patel
2902e378eb [CGP] add specialization for memcmp expansion with only one basic block
llvm-svn: 306485
2017-06-27 23:15:01 +00:00
Easwaran Raman
ba7953456e [NewPM/Inliner] Reduce threshold for cold callsites in the non-PGO case
Differential Revision: https://reviews.llvm.org/D34312

llvm-svn: 306484
2017-06-27 23:11:18 +00:00
Tim Northover
1182731c7c GlobalISel: add some more sanity-checking to MachineInstrBuilder. NFC.
llvm-svn: 306481
2017-06-27 22:45:35 +00:00
Florian Hahn
5722baf65f [AArch64] Inline callee if its target-features are a subset of the caller
Summary:
Similar to X86, it should be safe to inline callees if their target-features
are a subset of the caller. This change matches GCC's inlining behavior
with respect to attributes [1].

[1] https://gcc.gnu.org/onlinedocs/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes

Reviewers: kristof.beyls, javed.absar, rengolin, t.p.northover

Reviewed By: t.p.northover

Subscribers: aemerson, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D34698

llvm-svn: 306478
2017-06-27 22:27:32 +00:00
Geoff Berry
ee11ba5b52 [EarlyCSE][MemorySSA] Enable MemorySSA in function-simplification pass of EarlyCSE.
llvm-svn: 306477
2017-06-27 22:25:02 +00:00
Eugene Zelenko
3c80f475e7 [Analysis] Revert r306472 changes in LoopInfo headers to fix broken builds.
llvm-svn: 306476
2017-06-27 22:20:38 +00:00
Aditya Nandakumar
83ff413d56 [GISel]: Add G_FEXP, G_FEXP2 opcodes
Also add IRTranslator support.
https://reviews.llvm.org/D34710

llvm-svn: 306475
2017-06-27 22:19:32 +00:00
Rafael Espindola
753057d2fe clang-format a file.
It had a few inconsistent indentations that made a followup patch
hard to read.

llvm-svn: 306474
2017-06-27 22:14:20 +00:00
Dehao Chen
482aa8cd57 re-commit r306336: Enable vectorizer-maximize-bandwidth by default.
Differential Revision: https://reviews.llvm.org/D33341

llvm-svn: 306473
2017-06-27 22:05:58 +00:00
Eugene Zelenko
f4dfd3eed3 [Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 306472
2017-06-27 21:52:05 +00:00
Sanjay Patel
3e73231abb [CGP] eliminate a sub instruction in memcmp expansion
As noted in D34071, there are some IR optimization opportunities that could be 
handled by normal IR passes if this expansion wasn't happening so late in CGP.

Regardless of that, it seems wasteful to knowingly produce suboptimal IR here, 
so I'm proposing this change:
  %s = sub i32 %x, %y
  %r = icmp ne %s, 0
    =>
  %r = icmp ne %x, %y

Changing the predicate to 'eq' mimics what InstCombine would do, so that's just
an efficiency improvement if we decide this expansion should happen sooner.

The fact that the PowerPC backend doesn't eliminate the 'subf.' might be 
something for PPC folks to investigate separately.

Differential Revision: https://reviews.llvm.org/D34416

llvm-svn: 306471
2017-06-27 21:46:34 +00:00
Tim Northover
e8c4bdecf5 GlobalISel: verify that a COPY is trivial when created.
Without this check, COPY instructions can actually be one of the generic casts
in disguise. That's confusing and bad.

At some point during ISel this restriction has to be relaxed since the fully
selected instructions will usually use COPY for those purposes. Right now I
think it's possible that relaxation occurs during RegBankSelect (hence the
change there). I'm not convinced that's where it belongs long-term though.

llvm-svn: 306470
2017-06-27 21:41:40 +00:00
Xinliang David Li
5fe7317bf3 Clean up a test case
llvm-svn: 306468
2017-06-27 21:35:49 +00:00
Krzysztof Parzyszek
5f0aaebcf6 Create a PHI value when merging with a known undef live-in
Differential Revision: https://reviews.llvm.org/D34640

llvm-svn: 306466
2017-06-27 21:30:46 +00:00
Sam Clegg
3c8731e773 [WebAssembly] Only run WebAssembly objdump tests if it is enabled as a target
Differential Revision: https://reviews.llvm.org/D34712

llvm-svn: 306464
2017-06-27 21:19:27 +00:00
Joel Jones
59c2934bb3 [AArch64] Performance enhancements for Cavium ThunderX2 T99
This patch enables significant performance enhancements to the
Cavium ThunderX2T99 LLVM backend, as observed by running SPEC2K6,
by adding more detailed scheduling information.

Related Bugzilla bug: http://bugs.llvm.org/show_bug.cgi?id=32562

Patch by: steleman

Differential Revision: https://reviews.llvm.org/D31801

llvm-svn: 306462
2017-06-27 20:44:55 +00:00
Sam Clegg
6392bbbc67 [WebAssembly] Add support for printing relocations with llvm-objdump
Differential Revision: https://reviews.llvm.org/D34658

llvm-svn: 306461
2017-06-27 20:40:53 +00:00
Sam Clegg
d3b03d52bc [WebAssembly] Add data size and alignement to linking section
The overal size of the data section (including BSS)
is otherwise not included in the wasm binary.

Differential Revision: https://reviews.llvm.org/D34657

llvm-svn: 306459
2017-06-27 20:27:59 +00:00
Krzysztof Parzyszek
6a67a4e40b [Hexagon] Use proper predicate register state when expanding PS_vselect
llvm-svn: 306458
2017-06-27 19:59:46 +00:00
Craig Topper
5f5b183c10 [InstCombine] Propagate nsw flag when turning mul by pow2 into shift when the constant is a vector splat or the scalar bit width is larger than 64-bits
The check to see if we can propagate the nsw flag used m_ConstantInt(uint64_t*&) which doesn't work with splat vectors and has a restriction that the bitwidth of the ConstantInt must be 64-bits are less.

This patch changes it to use m_APInt to remove both these issues

Differential Revision: https://reviews.llvm.org/D34699

llvm-svn: 306457
2017-06-27 19:57:53 +00:00
Craig Topper
8a32d3ce9a [Constants] Fix copy-pasto in llvm_unreachable message. NFC
llvm-svn: 306456
2017-06-27 19:57:51 +00:00
Sanjay Patel
3175626c72 [CGP] simplify code to get bswap in memcmp expansion; NFCI
llvm-svn: 306452
2017-06-27 19:31:35 +00:00
Stanislav Mekhanoshin
da0aa39c03 [AMDGPU] Add 2 new alignbit patterns
Differential Revision: https://reviews.llvm.org/D34655

llvm-svn: 306449
2017-06-27 19:10:47 +00:00
Serge Guelton
5b6d0c63f5 [CodeExtractor] Prevent extraction of block involving blockaddress
BlockAddress are only valid within their function context, which does not
interact well with CodeExtractor. Detect this case and prevent it.

Differential Revision: https://reviews.llvm.org/D33839

llvm-svn: 306448
2017-06-27 18:57:53 +00:00
Stanislav Mekhanoshin
9d3604967f [AMDGPU] Simplify setcc (sext from i1 b), -1|0, cc
Depending on the compare code that can be either an argument of
sext or negate of it. This helps to avoid v_cndmask_b64 instruction
for sext. A reversed value can be further simplified and folded into
its parent comparison if possible.

Differential Revision: https://reviews.llvm.org/D34545

llvm-svn: 306446
2017-06-27 18:53:03 +00:00
Krzysztof Parzyszek
840728b581 [Hexagon] Update kills in hexagon-nvj even more properly than before
Account for the fact that both, the feeder and the compare can be moved
over instructions that kill registers.

llvm-svn: 306443
2017-06-27 18:37:16 +00:00
Matt Arsenault
b4e591cd6e RenameIndependentSubregs: Fix infinite loop
Apparently this replacement can really be substituting the
same as the original register. Avoid restarting the loop
when there's been no change in the register uses.

llvm-svn: 306441
2017-06-27 18:28:10 +00:00
Yaxun Liu
cdd653e805 [SROA] Fix APInt size when alloca address space is not 0
SROA assumes alloca address space is 0, which causes assertion. This patch fixes that.

Differential Revision: https://reviews.llvm.org/D34104

llvm-svn: 306440
2017-06-27 18:26:06 +00:00
Stanislav Mekhanoshin
f85be265f1 [AMDGPU] Combine and x, (sext cc from i1) => select cc, x, 0
Also factored out function to check if a boolean is an already
deserialized value which does not require v_cndmask_b32 to be
loaded. Added binary logical operators to its check.

Differential Revision: https://reviews.llvm.org/D34500

llvm-svn: 306439
2017-06-27 18:25:26 +00:00
Sanjay Patel
e4d3650f6b [CGP] add an IR builder to memcmp expansion class instead of recreating it; NFCI
This was a clean-up suggestion from:
https://reviews.llvm.org/D34005

llvm-svn: 306438
2017-06-27 18:18:42 +00:00
Jakub Kuderski
1b1056602a [Dominators] Use Semi-NCA instead of SLT to calculate dominators
Summary:
This patch makes GenericDomTreeConstruction use the Semi-NCA algorithm instead of Simple Lengauer-Tarjan.

As described in `RFC: Dynamic dominators`, Semi-NCA offers slightly better performance than SLT. What's more important, it can be extended to perform incremental updates on already constructed dominator trees.

The patch passes check-all, llvm test suite and is able to boostrap clang. I also wasn't able to observe any compilation time regressions.

Reviewers: sanjoy, dberlin, chandlerc, grosser

Reviewed By: dberlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34258

llvm-svn: 306437
2017-06-27 18:08:53 +00:00
Matthias Braun
f32356fc1f LiveRangeCalc: Slightly improve map usage; NFC
- DenseMap should be faster than std::map
- Use the `InsertRes = insert() if (!InsertRes.inserted)` pattern rather
  than the `if (!X.contains(...)) { X.insert(...); }` to save one map
  lookup.

llvm-svn: 306436
2017-06-27 18:05:26 +00:00
Sanjay Patel
f07531ee05 [InstCombine] canonicalize icmp predicate feeding select
This canonicalization was suggested in D33172 as a way to make InstCombine behavior more uniform. 
We have this transform for icmp+br, so unless there's some reason that icmp+select should be 
treated differently, we should do the same thing here.

The benefit comes from increasing the chances of creating identical instructions. This is shown in
the tests in logical-select.ll (PR32791). InstCombine doesn't fold those directly, but EarlyCSE 
can simplify the identical cmps, and then InstCombine can fold the selects together.

The possible regression for the tests in select.ll raises questions about poison/undef:
http://lists.llvm.org/pipermail/llvm-dev/2017-May/113261.html

...but that transform is just as likely to be triggered by this canonicalization as it is to be 
missed, so we're just pointing out a commutation deficiency in the pattern matching:
https://reviews.llvm.org/rL228409

Differential Revision: https://reviews.llvm.org/D34242

llvm-svn: 306435
2017-06-27 17:53:22 +00:00
Dehao Chen
b4a118c189 Enable ICP for AutoFDO.
Summary: AutoFDO should have ICP enabled.

Reviewers: davidxl

Reviewed By: davidxl

Subscribers: sanjoy, mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D34662

llvm-svn: 306429
2017-06-27 17:23:33 +00:00
Xinliang David Li
e12318bace [ProfData] Make the method threadsafe
llvm-svn: 306428
2017-06-27 17:21:51 +00:00
Craig Topper
dd736da225 [InstCombine] Add test case demonstrating that we don't propagate nsw flag when converting mul by pow2 to shl when the type is larger than 64-bits. NFC
llvm-svn: 306427
2017-06-27 17:16:03 +00:00
Craig Topper
aa24605f0f [InstCombine] Add test cases to show that we don't propagate 'nsw' flags when converting mul by pow2 constant to shl for splat vectors. NFC
llvm-svn: 306426
2017-06-27 17:16:01 +00:00
Coby Tayree
fde297e160 [X86][AsmParser][MS-compatability] Binary/Unary operators enhancements
Introducing MOD binary operator
https://msdn.microsoft.com/en-us/library/hha180wt.aspx

Enhancing unary operators NEG and NOT, to support more complex patterns

Differential Revision: https://reviews.llvm.org/D33876

llvm-svn: 306425
2017-06-27 16:58:27 +00:00