Eric Christopher
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70a4ec2213
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In preparation for moving ARM's TargetRegisterInfo to the TargetMachine
merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable
us to match the TargetMachine for our TargetRegisterInfo classes.
llvm-svn: 232117
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2015-03-12 22:48:50 +00:00 |
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James Molloy
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a4b2ec478f
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Fix the Load/Store optimization pass to work with Thumb1.
Patch by Moritz Roth!
llvm-svn: 208992
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2014-05-16 14:14:30 +00:00 |
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Gordon Keiser
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0c0f300008
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Testing commit access to llvm. Remove two lines of whitespace from the Thumb README.
llvm-svn: 178256
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2013-03-28 18:26:15 +00:00 |
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Nick Lewycky
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fb3f7c11f1
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Add another note taken from the gcc bugzilla.
llvm-svn: 123315
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2011-01-12 09:06:19 +00:00 |
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Jim Grosbach
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ea6c9c17f5
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Use Unified Assembly Syntax for the ARM backend.
llvm-svn: 86494
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2009-11-09 00:11:35 +00:00 |
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Jim Grosbach
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2fb5eb1264
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Enable allocation of R3 in Thumb1
llvm-svn: 84563
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2009-10-19 22:57:03 +00:00 |
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Evan Cheng
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e3a37c42fb
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Another TODO.
llvm-svn: 77026
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2009-07-25 00:39:37 +00:00 |
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Evan Cheng
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2125e12632
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Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c.
llvm-svn: 76401
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2009-07-20 06:59:32 +00:00 |
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Evan Cheng
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03d981d91b
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Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
llvm-svn: 75360
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2009-07-11 07:08:13 +00:00 |
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Evan Cheng
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268b47b1fb
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Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
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2009-07-11 06:43:01 +00:00 |
|
Evan Cheng
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6e276f4376
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More info about Thumb1 predication support.
llvm-svn: 75220
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2009-07-10 02:10:17 +00:00 |
|
Evan Cheng
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0d509459ff
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Another todo entry.
llvm-svn: 75192
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2009-07-09 23:17:28 +00:00 |
|
Evan Cheng
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7f8e728a54
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Add a Thumb readme entry.
llvm-svn: 75173
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2009-07-09 20:50:52 +00:00 |
|
Jim Grosbach
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df52e6897d
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Whitespace cleanup. Test commit.
llvm-svn: 54695
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2008-08-12 18:34:45 +00:00 |
|
Evan Cheng
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252d9ddb4d
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Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
llvm-svn: 43234
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2007-10-22 22:11:27 +00:00 |
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Chris Lattner
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8a38eebb69
|
update this entry, now that Anton implemented shift/and lowering for
switches. There is one really easy isel thing here with tst we are not
getting.
llvm-svn: 37400
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2007-06-02 18:45:14 +00:00 |
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Evan Cheng
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526a67c09b
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New entry.
llvm-svn: 35480
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2007-03-29 21:40:13 +00:00 |
|
Evan Cheng
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11976abd1e
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New entry.
llvm-svn: 35206
|
2007-03-20 08:10:17 +00:00 |
|
Evan Cheng
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808cf2b6a1
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New entry.
llvm-svn: 34000
|
2007-02-07 09:22:15 +00:00 |
|
Evan Cheng
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8f5c613d03
|
Update
llvm-svn: 33998
|
2007-02-07 08:37:57 +00:00 |
|
Evan Cheng
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60bde0ebb1
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Spill / restore should avoid modifying the condition register.
llvm-svn: 33971
|
2007-02-07 00:06:56 +00:00 |
|
Evan Cheng
|
eafe1f7bd9
|
Add a note.
llvm-svn: 33743
|
2007-02-01 02:46:20 +00:00 |
|
Evan Cheng
|
3d8d381600
|
Possible JT improvements.
llvm-svn: 33733
|
2007-02-01 01:07:48 +00:00 |
|
Evan Cheng
|
0ce094c7a8
|
Add entry.
llvm-svn: 33723
|
2007-01-31 22:11:38 +00:00 |
|
Evan Cheng
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e0dc07a83f
|
New entry.
llvm-svn: 33569
|
2007-01-27 02:33:22 +00:00 |
|
Evan Cheng
|
c6e1d453d3
|
ARM backend contribution from Apple.
llvm-svn: 33353
|
2007-01-19 07:51:42 +00:00 |
|