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Commit Graph

192587 Commits

Author SHA1 Message Date
Sjoerd Meijer
ff9f01c06e [AArch64] Peephole optimization: merge AND and TST instructions
In some cases Clang does not perform merging of instructions AND and TST (aka
ANDS xzr).

Example:

  tst x2, x1
  and x3, x2, x1

to:

  ands x3, x2, x1

This patch add such merging during instruction selection: when AND is replaced
with ANDS instruction in LowerSELECT_CC, all users of AND also should be
changed for using this ANDS instruction

Short discussion on mailing list:
http://llvm.1065342.n5.nabble.com/llvm-dev-ARM-Peephole-optimization-instructions-tst-add-tp133109.html

Patch by Pavel Kosov.

Differential Revision: https://reviews.llvm.org/D71701
2020-02-27 09:23:47 +00:00
Nemanja Ivanovic
7f3f3aa402 Fix buildbot break after c46b85aaf4d4
I added test cases that rely on the availability of the PPC target into
the general directory for the loop vectorizer. This causes failures on
bots that don't build the PPC target. Moving them to the PowerPC directory
to fix this.
2020-02-26 21:56:11 -06:00
Nemanja Ivanovic
443db462fa [LoopVectorize] Fix cost for calls to functions that have vector versions
A recent commit
(https://reviews.llvm.org/rG66c120f02560ef528a60924104ead66f330190f1) changed
the cost for calls to functions that have a vector version for some
vectorization factor. However, no check is performed for whether the
vectorization factor matches the current one being cost modeled. This leads to
attempts to widen call instructions to a vectorization factor for which such a
function does not exist, which in turn leads to an assertion failure.

This patch adds the check for vectorization factor (i.e. not just that the
called function has a vector version for some VF, but that it has a vector
version for this VF).

Differential revision: https://reviews.llvm.org/D74944
2020-02-26 21:39:11 -06:00
Matt Arsenault
d6b09fcd65 AMDGPU/GlobalISel: Add missing test for G_UMULH 2020-02-26 22:30:13 -05:00
Matt Arsenault
42e31807bb GlobalISel: Fix lowering for G_UADDE/G_USUBE
The type parameter passed into lower is invalid and should be removed
from the function.
2020-02-26 19:10:52 -08:00
Matt Arsenault
9e317ebc36 AMDGPU/GlobalISel: Add missing G_[US]ADDE/G_[US]SUBE tests
The s64 case currently crashes, so leave that for later.
2020-02-26 19:10:34 -08:00
Matt Arsenault
def8c6c670 GlobalISel: Cleanup code with MachineIRBuilder features 2020-02-26 19:10:34 -08:00
Stefanos Baziotis
371dde815e [docs][LoopTerminology] Add Loop Simplify Form description.
Information taken from https://youtu.be/3pRhvQi7Z10?t=481 and
comments in LoopSimplify.h.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D74989
2020-02-26 20:41:06 -06:00
Craig Topper
5b55f85415 [X86] Add test cases showing incorrect setting of nofpexcept flag due to CSE occuring during SelectionDAG creation.
These tests generate two nodes that are identical except for the
metadata that indicates their exception behavior. The nodes get
CSEd by SelectionDAG, but the nofpexcept flag is being set based
only on the fpexcept.ignore node being created last.

We need to detect this case and intersect the flags similar to
what is already done with fast math flags.
2020-02-26 18:10:27 -08:00
Kirill Naumov
50da41c112 Cost Annotation Writer for InlineCost
Add extra diagnostics for the inline cost analysis under
-print-instruction-deltas cl option. When enabled along with
-debug-only=inline-cost it prints the IR of inline candidate
annotated with cost and threshold change per every instruction.

Reviewed By: apilipenko, davidxl, mtrofin

Differential Revision: https://reviews.llvm.org/D71501
2020-02-26 17:03:52 -08:00
Craig Topper
a250731532 [X86] Add proper MachinePointerInfo to stack store created in LowerWin64_i128OP. 2020-02-26 16:55:24 -08:00
Craig Topper
247f178404 [X86] Explicitly pass Destination VT and debug location to BuildFILD. NFC
We'd already passed most everything else. Might was well pass
these two things and stop passing Op.
2020-02-26 16:26:46 -08:00
Craig Topper
c4f5d59862 [X86] Explicitly pass Pointer, MachinePointerInfo and Alignment to BuildFILD.
Previously this code was called into two ways, either a FrameIndexSDNode
was passed in StackSlot. Or a load node was passed in the argument
called StackSlot. This was determined by a dyn_cast to FrameIndexSDNode.

In the case of a load, we had to go find the real pointer from
operand 0 and cast the node to MemSDNode to find the pointer info.

For the stack slot case, the code assumed that the stack slot
was perfectly aligned despite not being the creator of the slot.

This commit modifies the interface to make the caller responsible
for passing all of the required information to avoid all the
guess work and reverse engineering.

I'm not aware of any issues with the original code after an
earlier commit to fix the alignment of one of the stack objects.
This is just clean up to make the code less surprising.
2020-02-26 16:26:26 -08:00
Erik Pilkington
72e9f2a47d Disable memory leak checking in a test to work around a bot failure
This leak is expected, see the discussion on commit 85fb997
2020-02-26 14:51:50 -08:00
Adrian Prantl
a3cf46e4b5 Visit previously unreachable nodes in the debug info metadata verifier.
This allows for diagnosing malformed LLVM IR debug info metadata such
as the one in the testcase.

<rdar://problem/59756060>

Differential Revision: https://reviews.llvm.org/D75212
2020-02-26 14:48:08 -08:00
Craig Topper
2ffb2b7c4e [X86] Query constant pool object alignment instead of hardcoding. 2020-02-26 14:45:39 -08:00
Craig Topper
e0577cb55d [X86] Use proper alignment for stack temporary and correct MachinePointerInfo for stack accesses in LowerUINT_TO_FP. 2020-02-26 14:45:38 -08:00
Craig Topper
8a31a23654 [X86] Use correct MachineMemOperand for stack load in LowerFLT_ROUNDS_ 2020-02-26 14:45:38 -08:00
Craig Topper
c49b54369d [X86] Add proper MachinePointerInfo to the loads/stores created for moving data between SSE and X87 in X86DAGToDAGISel::PreprocessISelDAG 2020-02-26 14:45:37 -08:00
Amara Emerson
aa8fb00f42 [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection.
Since all types <32b on gpr end up being assigned gpr32 regclasses, we can end
up with PHIs here which try to select between a gpr32 and an fpr16. Ideally RBS
shouldn't be selecting heterogenous regbanks for operands if possible, but we
still need to be able to deal with it here.

To fix this, if we have a gpr-bank operand < 32b in size and at least one other
operand is on the fpr bank, then we add cross-bank copies to homogenize the
operand banks. For simplicity the bank that we choose to settle on is whatever
bank the def operand has. For example:

%endbb:
  %dst:gpr(s16) = G_PHI %in1:gpr(s16), %bb1, %in2:fpr(s16), %bb2
 =>
%bb2:
  ...
  %in2_copy:gpr(s16) = COPY %in2:fpr(s16)
  ...
%endbb:
  %dst:gpr(s16) = G_PHI %in1:gpr(s16), %bb1, %in2_copy:gpr(s16), %bb2

Differential Revision: https://reviews.llvm.org/D75086
2020-02-26 14:10:32 -08:00
Alexey Lapshin
7caf79acd9 [DebugInfo][NFC] Remove handler with ErrorPolicy from DWARFContext.
Summary:
Current LLVM code base does not use error handler with ErrorPolicy.
This patch removes ErrorPolicy from DWARFContext.

This patch is extracted from the D74308.

Reviewers: jhenderson, dblaikie, grimar, aprantl, JDevlieghere

Reviewed By: grimar

Subscribers: hiraditya, llvm-commits

Tags: #llvm, #debug-info

Differential Revision: https://reviews.llvm.org/D75118
2020-02-27 00:42:37 +03:00
Philip Reames
d3bebc4ca9 [MC] Pull out a relaxFragment helper [NFC]
Having this as it's own function helps to reduce indentation and allows use of return instead of wiring a value over the switch.  A lambda would have also worked, but with slightly deeper nesting.
2020-02-26 13:37:12 -08:00
Alexander Shaposhnikov
f507c7164f [llvm-objcopy] Enable --discard-all for MachO
In this diff we enable the option --discard-all for MachO.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D75104
2020-02-26 12:51:15 -08:00
Adrian Prantl
53c8ce0f6c [dsymutil] Avoid copying swiftinterfaces from the SDK into the dsym bundle
This patch fixes a bug that would cause dsymutil to collect
.swiftinterface files for the Swift stdlib and other SDK
modules. There is no advantage in copying these since they should be
loaded from the ones bundled with LLDB's embedded Swift compiler
instead and copying them will cause LLDB to recompile them from source
instead of loading their prebuilt cached counterparts in the SDK.

rdar://problem/57463247

Differential Revisions: https://reviews.llvm.org/D75196
2020-02-26 12:22:50 -08:00
Eric Astor
16733cfe07 [ms] Rename ParsingInlineAsm functions/variables to reflect MS-specificity.
Summary: ParsingInlineAsm was a misleading name. These values are only set for MS-style inline assembly.

Reviewed By: rnk

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D75198
2020-02-26 15:19:40 -05:00
Sanjay Patel
98b9a418a9 [VectorCombine] add a debug flag to skip all transforms
As suggested in D75145 -

I'm not sure why, but several passes have this kind of disable/enable flag
implemented at the pass manager level. But that means we have to duplicate
the flag for both pass managers and add code to check the flag every time
the pass appears in the pipeline.

We want a debug option to see if this pass is misbehaving regardless of the
pass managers, so just add a disablement check at the single point before
any transforms run.

Differential Revision: https://reviews.llvm.org/D75204
2020-02-26 15:15:42 -05:00
Nikita Popov
4c11fe03d8 [SimpleLoopUnswitch] Remove unnecessary include; NFC 2020-02-26 20:40:43 +01:00
Nikita Popov
99f935f7df [CVP] Simplify cmp of local phi node
CVP currently does not simplify cmps with instructions in the same
block, because LVI getPredicateAt() currently does not provide
much useful information for that case (D69686 would change that,
but is stuck.) However, if the instruction is a Phi node, then
LVI can compute the result of the predicate by threading it into
the predecessor blocks, which allows it simplify some conditions
that nothing else can handle. Relevant code:
6d6a4590c5/llvm/lib/Analysis/LazyValueInfo.cpp (L1904-L1927)

Differential Revision: https://reviews.llvm.org/D72169
2020-02-26 20:36:41 +01:00
Nikita Popov
8852d5e0e5 [InstCombine] Simplify DCE code; NFC
As pointed out on D75008, MadeIRChange is already set by
eraseInstFromFunction(), which also already does a debug print.
2020-02-26 20:33:00 +01:00
Nikita Popov
bd78c41ca6 [CVP] Add test for cmp of local phi; NFC 2020-02-26 20:32:59 +01:00
Ayke van Laethem
8f4cb72386 [AVR] Fix private label prefix
This is a small pet peeve from me. This change makes sure the AVR backend uses
the correct private label prefix (.L) so that private labels are hidden in
avr-objdump.

Example code:

    define i8 @foo(i1 %cond) {
      br i1 %cond, label %then, label %else
    then:
      ret i8 3
    else:
      ret i8 5
    }

When compiling this:
  llc -march=avr -filetype=obj -o test.o test.ll
and then dumping it:
  avr-objdump -d test.o
You would previously get an ugly temporary label:

    00000000 <foo>:
       0:        81 70       andi       r24, 0x01    ; 1
       2:        80 30       cpi        r24, 0x00    ; 0
       4:        f9 f3       breq       .-2          ; 0x4 <foo+0x4>
       6:        83 e0       ldi        r24, 0x03    ; 3
       8:        08 95       ret

    0000000a <LBB0_2>:
       a:        85 e0       ldi        r24, 0x05    ; 5
       c:        08 95       ret

This patch fixes that, the output is now:

    00000000 <foo>:
       0:        81 70       andi       r24, 0x01    ; 1
       2:        80 30       cpi        r24, 0x00    ; 0
       4:        01 f0       breq       .+0          ; 0x6 <foo+0x6>
       6:        83 e0       ldi        r24, 0x03    ; 3
       8:        08 95       ret
       a:        85 e0       ldi        r24, 0x05    ; 5
       c:        08 95       ret

Note that as you can see the breq operand is different. However it is
still the same after linking:

       4:        11 f0       breq       .+4

Differential Revision: https://reviews.llvm.org/D75124
2020-02-26 20:32:25 +01:00
Ayke van Laethem
350598f8a1 [AVR] Don't adjust addresses by 2 for absolute values
Adjusting by 2 breaks DWARF output. With this fix, programs start to
compile and produce valid DWARF output.

Differential Revision: https://reviews.llvm.org/D74213
2020-02-26 20:32:24 +01:00
Nikita Popov
abfdd395ea [InstCombine] Remove trivially empty ranges from end
InstCombine removes pairs of start+end intrinsics that don't
have anything in between them. Currently this is done by starting
at the start intrinsic and scanning forwards. This patch changes
it to start at the end intrinsic and scan backwards.

The motivation here is as follows: When we process the start
intrinsic, we have not yet looked at the following instructions,
which may still get folded/removed. If they do, we will only be
able to remove the start/end pair on the next iteration. When we
process the end intrinsic, all the instructions before it have
already been visited, and we don't run into this problem.

Differential Revision: https://reviews.llvm.org/D75011
2020-02-26 20:04:11 +01:00
Reid Kleckner
fcf92d4a71 Fix LLP64 detection in SwapByteOrder.h
MSVC does not define __LONG_MAX__, so we were just getting lucky in this
conditional:
  #if __LONG_MAX__ == __INT_MAX__

Undefined identifiers evaluate to zero in preprocessor conditionals, so
this became true, which happens to work for MSVC platforms.

Instead, use this pattern and let the compiler constant fold:
  return sizeof(long) == sizeof(int) ? SwapByteOrder_32((uint32_t)C)
                                     : SwapByteOrder_64((uint64_t)C);
2020-02-26 10:59:45 -08:00
Krzysztof Parzyszek
7752ba906a [Hexagon] Improve casting of boolean HVX vectors to scalars
- Mark memory access for bool vectors as disallowed in target lowering.
  This will prevent combining bitcasts of bool vectors with stores.
- Replace the actual bitcasting code with a faster version.
- Handle casting of v16i1 to i16.
2020-02-26 12:46:52 -06:00
Reid Kleckner
d5b09af4ad Remove unneeded Compiler.h and DataTypes.h includes, NFC 2020-02-26 10:36:17 -08:00
Greg Clayton
a5746e4e18 Fix buildbots after recent GSYM commit.
Added llvm-gsymutil to LLVM_TEST_DEPENDS.
2020-02-26 10:30:04 -08:00
Krzysztof Parzyszek
02cb3d14a2 [SDAG] Add SDNode::values() = make_range(values_begin(), values_end())
Also use it in a few places to simplify code a little bit.  NFC
2020-02-26 12:07:38 -06:00
Juneyoung Lee
0958192882 [TTI] Let getOperationCost assume that Freeze is free 2020-02-27 02:56:11 +09:00
Hiroshi Yamauchi
017c178b5d Devirtualize a call on alloca without waiting for post inline cleanup and next
DevirtSCCRepeatedPass iteration.  Needs ReviewPublic

This aims to fix a missed inlining case.

If there's a virtual call in the callee on an alloca (stack allocated object) in
the caller, and the callee is inlined into the caller, the post-inline cleanup
would devirtualize the virtual call, but if the next iteration of
DevirtSCCRepeatedPass doesn't happen (under the new pass manager), which is
based on a heuristic to determine whether to reiterate, we may miss inlining the
devirtualized call.

This enables inlining in clang/test/CodeGenCXX/member-function-pointer-calls.cpp.
2020-02-26 09:51:24 -08:00
Sean Fertile
6050aa4c53 [PowerPC][NFC] Convert grep usage to FileCheck in lit test. 2020-02-26 12:28:18 -05:00
Reid Kleckner
8e3a06ab38 Avoid SmallString.h include in MD5.h, NFC
Saves 200 includes, which is mostly immaterial.
2020-02-26 09:10:24 -08:00
Fangrui Song
7263503150 [llvm-objcopy][test] Improve empty section tests
empty-sections.test: add two tests adapted from @jhenderson's https://reviews.llvm.org/D74755#1882221
strip-non-alloc.test: improve. D74755 will change the attribution of an empty section.

They mostly test the behavior of Object.cpp:sectionWithinSegment : how we attribute sections to segments.
`ParentSegment` can affect some subtle layout decisions.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D74879
2020-02-26 08:57:23 -08:00
Sanjay Patel
2a134853e7 [DAGCombiner] avoid narrowing fake fneg vector op
This may inhibit vector narrowing in general, but there's
already an inconsistency in the way that we deal with this
pattern as shown by the test diff.

We may want to add a dedicated function for narrowing fneg.
It's often folded into some other op, so moving it away from
other math ops may cause regressions that we would not see
for normal binops.

See D73978 for more details.
2020-02-26 11:25:56 -05:00
LLVM GN Syncbot
6b398fe33b [gn build] Port 3c36d8dad57 2020-02-26 16:09:48 +00:00
Pavel Labath
2993a0fb59 Introduce DWARFDataExtractor::getInitialLength
Summary:
This patch introduces a function to house the code needed to do the
DWARF64 detection dance. The function decodes the initial length field
and returns it as a pair containing the actual length, and the DWARF
encoding.

This patch does _not_ attempt to handle the problem of detecting lengths
which extend past the size of the section, or cases when reads of a
single contribution accidentally escape beyond its specified length, but
I think it's useful in its own right.

Reviewers: dblaikie, jhenderson, ikudrin

Subscribers: hiraditya, probinson, aprantl, JDevlieghere, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74560
2020-02-26 17:07:58 +01:00
Sanjay Patel
4df15e04a9 [AArch64] add tests for fake fneg; NFC
See comments in D73978 for background.
2020-02-26 10:56:26 -05:00
Simon Pilgrim
8c779f8acd [DAG] visitRotate - modulo non-uniform constant rotation amounts 2020-02-26 15:43:12 +00:00
Pavel Labath
87036fd412 Recommit "[DWARFDebugLine] Avoid dumping prologue members we did not parse"
The patch was reverted in 69da40033 because of test failures on windows.
The problem was the unpredictable order of some of the error messages,
which I've tried to strenghten in that patch.

It turns out this is not possible to do in verbose mode because there
the data is being writted as it is being parsed. No amount of flushing
(as I've done in the non-verbose mode) will help that. Indeed, even
without any buffering the warning messages can end in the middle of a
line in non-verbose mode.

In this patch, I have reverted the changes which tested the relative
position of the warning message, except for the messages about
unsupported initial length, which are the ones I really wanted to test,
and which do come out reasonably.

The original commit message was:

This patch if motivated by D74560, specifically the subthread about what
to print upon encountering reserved initial length values.

If the debug_line prologue has an unsupported version, we skip parsing
the rest of the data. If we encounter an reserved initial length field,
we don't even parse the version. However, we still print out all members
(with value 0) in the dump function.

This patch introduces early exits in the Prologue::dump function so that
we print only the fields that were parsed successfully. In case of an
unsupported version, we skip printing all subsequent prologue fields --
because we don't even know if this version has those fields. In case of a
reserved unit length, we don't print anything -- if the very first field
of the prologue is invalid, it's hard to say if we even have a prologue
to begin with.

Note that the user will still be able to see the invalid/reserved
initial length value in the error message. I've modified (reordered)
debug_line_invalid.test to show that the error message comes straight
after the debug_line offset. I've also added some flush() calls to the
dumping code to ensure this is the case in all situations (without that,
the warnings could get out of sync if the output was not a terminal -- I
guess this is why std::iostreams have the tie() function).

Reviewers: jhenderson, ikudrin, dblaikie

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75043
2020-02-26 16:42:25 +01:00
Nicolai Hähnle
5308258af1 Full fix for "AMDGPU/SIInsertSkips: Fix the determination of whether early-exit-after-kill is possible" (hopefully)
Properly preserve the MachineDominatorTree in all cases.

Change-Id: I54cf0c0a20934168a356920ba8ed5097a93c4131
2020-02-26 16:21:44 +01:00