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Commit Graph

237 Commits

Author SHA1 Message Date
Owen Anderson
ffb049d199 Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
llvm-svn: 137787
2011-08-16 23:45:44 +00:00
Owen Anderson
2e722e7cd4 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
llvm-svn: 137686
2011-08-15 23:38:54 +00:00
Owen Anderson
42946000dd Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
Patch by James Molloy.

llvm-svn: 137647
2011-08-15 20:51:32 +00:00
Owen Anderson
894585de33 Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
llvm-svn: 137635
2011-08-15 18:44:44 +00:00
Owen Anderson
2ea55a0881 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
Owen Anderson
7b426d97ad Fix decoding of ARM-mode STRH.
llvm-svn: 137499
2011-08-12 20:02:50 +00:00
Owen Anderson
322b9ce8bf Fix decoding of pre-indexed stores.
llvm-svn: 137487
2011-08-12 18:12:39 +00:00
Owen Anderson
a1df383bae Separate decoding for STREXD and LDREXD to make each work better.
llvm-svn: 137476
2011-08-12 17:58:32 +00:00
Jim Grosbach
edefbb31c3 ARM STRT assembly parsing and encoding.
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
Owen Anderson
8a55a4d7be Add another accidentally omitted predicate operand.
llvm-svn: 137370
2011-08-11 22:08:38 +00:00
Owen Anderson
253a691ae5 Add missing predicate operand on SMLA and friends.
llvm-svn: 137368
2011-08-11 22:05:38 +00:00
Owen Anderson
64c500c7dd Fix decoding support for STREXD and LDREXD.
llvm-svn: 137356
2011-08-11 21:34:58 +00:00
Owen Anderson
4618d77bcd Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
Owen Anderson
73e7d34732 Continue to tighten decoding by performing more operand validation.
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Jim Grosbach
bfc85134c2 ARM STRBT assembly parsing and encoding.
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
Owen Anderson
63ccfdccd1 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
Owen Anderson
decc5fcced Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
Owen Anderson
8d6b9f063f Improve error checking in the new ARM disassembler. Patch by James Molloy.
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
Jim Grosbach
5322f1ea74 ARM LDRT assembly parsing and encoding.
llvm-svn: 137282
2011-08-10 23:43:54 +00:00
Owen Anderson
0fde7a84ee Add initial support for decoding NEON instructions in Thumb2 mode.
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
Owen Anderson
0819cf208f Cleanups based on Nick Lewycky's feedback.
llvm-svn: 137224
2011-08-10 17:36:48 +00:00
Owen Anderson
87b5ce880a Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
Owen Anderson
b717d71aa1 Tighten operand checking of register-shifted-register operands.
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
Owen Anderson
62faf296dd Tighten operand checking on memory barrier instructions.
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
Owen Anderson
869ce85500 Tighten operand checking on CPS instructions.
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
Owen Anderson
8ad37f68a2 Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Benjamin Kramer
ca48bdfd5b ARM Disassembler: sign extend branch immediates.
Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156
2011-08-09 22:02:50 +00:00
Owen Anderson
4232cf9141 Silence an false-positive warning.
llvm-svn: 137154
2011-08-09 21:38:14 +00:00
Owen Anderson
2aa4c7e391 Tighten Thumb1 branch predicate decoding.
llvm-svn: 137146
2011-08-09 21:07:45 +00:00
Owen Anderson
ffe1c55752 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Jim Grosbach
67621a1af4 ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

llvm-svn: 136969
2011-08-05 16:11:38 +00:00
Owen Anderson
11e2000c8c Fix broken encodings for the Thumb2 LDRD/STRD instructions.
llvm-svn: 136942
2011-08-04 23:18:05 +00:00
Jim Grosbach
767e9d16e6 ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Jim Grosbach
9f0533c5d2 ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Jim Grosbach
1b69dbc796 ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479
2011-07-29 18:47:24 +00:00
Chandler Carruth
f7890e34b9 Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

llvm-svn: 136433
2011-07-29 00:14:25 +00:00
Owen Anderson
086552069e Revert r136295. It broke nightly testers because some parts of codegen weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now.
llvm-svn: 136362
2011-07-28 17:18:57 +00:00
Owen Anderson
bf92556a9e Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first.
llvm-svn: 136295
2011-07-27 23:36:57 +00:00
Jim Grosbach
c5cd3228c4 ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264
2011-07-27 21:09:25 +00:00
Jim Grosbach
24aa0e7c2e ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.

llvm-svn: 136152
2011-07-26 21:28:43 +00:00
Chandler Carruth
a571c5d5d3 Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.

These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.

To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.

This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.

Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.

llvm-svn: 136023
2011-07-26 00:09:08 +00:00
Jim Grosbach
c1fe042da0 ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.

llvm-svn: 135990
2011-07-25 22:20:28 +00:00
Jim Grosbach
dd6b9fa0da ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.

llvm-svn: 135823
2011-07-22 23:16:18 +00:00
Jim Grosbach
bab60c95e1 Thumb assembly support for SETEND instruction.
llvm-svn: 135778
2011-07-22 17:52:23 +00:00
Owen Anderson
e34471d064 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
llvm-svn: 135722
2011-07-21 23:38:37 +00:00
Evan Cheng
bff5f78cb5 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
Jim Grosbach
572868e146 ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.

llvm-svn: 135626
2011-07-20 21:40:26 +00:00
Jim Grosbach
94a88152c9 ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.

llvm-svn: 135616
2011-07-20 20:32:09 +00:00
Owen Anderson
27021374f8 Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler.
llvm-svn: 135442
2011-07-18 23:25:34 +00:00
Owen Anderson
aadc53ca80 Re-apply r135319 with a fix for the constant island pass.
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135414
2011-07-18 18:50:52 +00:00