# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64-apple-ios"
  define void @test_rem() {
  entry:
    ret void
  }
...

---
name:            test_rem
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
  - { id: 8, class: _ }
  - { id: 9, class: _ }
  - { id: 10, class: _ }
body: |
  bb.0.entry:
    liveins: %x0, %x1, %x2, %x3

    ; CHECK: [[QUOT:%[0-9]+]](s64) = G_UDIV %0, %1
    ; CHECK: [[PROD:%[0-9]+]](s64) = G_MUL [[QUOT]], %1
    ; CHECK: [[RES:%[0-9]+]](s64) = G_SUB %0, [[PROD]]
    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s64) = G_UREM %0, %1

    ; CHECK: [[QUOT:%[0-9]+]](s32) = G_SDIV %3, %4
    ; CHECK: [[PROD:%[0-9]+]](s32) = G_MUL [[QUOT]], %4
    ; CHECK: [[RES:%[0-9]+]](s32) = G_SUB %3, [[PROD]]
    %3(s32) = G_TRUNC %0
    %4(s32) = G_TRUNC %1
    %5(s32) = G_SREM %3, %4

    ; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %6
    ; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %7
    ; CHECK: [[QUOT32:%[0-9]+]](s32) = G_SDIV [[LHS32]], [[RHS32]]
    ; CHECK: [[QUOT:%[0-9]+]](s8) = G_TRUNC [[QUOT32]]
    ; CHECK: [[PROD:%[0-9]+]](s8) = G_MUL [[QUOT]], %7
    ; CHECK: [[RES:%[0-9]+]](s8) = G_SUB %6, [[PROD]]
    %6(s8) = G_TRUNC %0
    %7(s8) = G_TRUNC %1
    %8(s8) = G_SREM %6, %7

    ; CHECK: %d0 = COPY %0
    ; CHECK: %d1 = COPY %1
    ; CHECK: BL $fmod, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
    ; CHECK: %9(s64) = COPY %d0
    %9(s64) = G_FREM %0, %1

    ; CHECK: %s0 = COPY %3
    ; CHECK: %s1 = COPY %4
    ; CHECK: BL $fmodf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
    ; CHECK: %10(s32) = COPY %s0
    %10(s32) = G_FREM %3, %4

...