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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
108 lines
4.3 KiB
C++
108 lines
4.3 KiB
C++
//===- llvm/CodeGen/SchedulerRegistry.h -------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation for instruction scheduler function
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// pass registry (RegisterScheduler).
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H
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#define LLVM_CODEGEN_SCHEDULERREGISTRY_H
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#include "llvm/CodeGen/MachinePassRegistry.h"
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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//===----------------------------------------------------------------------===//
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///
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/// RegisterScheduler class - Track the registration of instruction schedulers.
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///
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//===----------------------------------------------------------------------===//
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class ScheduleDAGSDNodes;
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class SelectionDAGISel;
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class RegisterScheduler
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: public MachinePassRegistryNode<
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ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level)> {
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public:
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using FunctionPassCtor = ScheduleDAGSDNodes *(*)(SelectionDAGISel*,
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CodeGenOpt::Level);
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static MachinePassRegistry<FunctionPassCtor> Registry;
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RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
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: MachinePassRegistryNode(N, D, C) {
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Registry.Add(this);
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}
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~RegisterScheduler() { Registry.Remove(this); }
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// Accessors.
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RegisterScheduler *getNext() const {
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return (RegisterScheduler *)MachinePassRegistryNode::getNext();
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}
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static RegisterScheduler *getList() {
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return (RegisterScheduler *)Registry.getList();
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}
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static void setListener(MachinePassRegistryListener<FunctionPassCtor> *L) {
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Registry.setListener(L);
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}
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};
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/// createBURRListDAGScheduler - This creates a bottom up register usage
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/// reduction list scheduler.
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ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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/// createBURRListDAGScheduler - This creates a bottom up list scheduler that
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/// schedules nodes in source code order when possible.
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ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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/// createHybridListDAGScheduler - This creates a bottom up register pressure
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/// aware list scheduler that make use of latency information to avoid stalls
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/// for long latency instructions in low register pressure mode. In high
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/// register pressure mode it schedules to reduce register pressure.
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ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level);
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/// createILPListDAGScheduler - This creates a bottom up register pressure
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/// aware list scheduler that tries to increase instruction level parallelism
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/// in low register pressure mode. In high register pressure mode it schedules
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/// to reduce register pressure.
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ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level);
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/// createFastDAGScheduler - This creates a "fast" scheduler.
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///
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ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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/// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
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/// DFA driven list scheduler with clustering heuristic to control
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/// register pressure.
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ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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/// createDefaultScheduler - This creates an instruction scheduler appropriate
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/// for the target.
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ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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/// createDAGLinearizer - This creates a "no-scheduling" scheduler which
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/// linearize the DAG using topological order.
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ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
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CodeGenOpt::Level OptLevel);
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} // end namespace llvm
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#endif // LLVM_CODEGEN_SCHEDULERREGISTRY_H
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