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5661b7eb80
This extends any frame record created in the function to include that parameter, passed in X22. The new record looks like [X22, FP, LR] in memory, and FP is stored with 0b0001 in bits 63:60 (CodeGen assumes they are 0b0000 in normal operation). The effect of this is that tools walking the stack should expect to see one of three values there: * 0b0000 => a normal, non-extended record with just [FP, LR] * 0b0001 => the extended record [X22, FP, LR] * 0b1111 => kernel space, and a non-extended record. All other values are currently reserved. If compiling for arm64e this context pointer is address-discriminated with the discriminator 0xc31a and the DB (process-specific) key. There is also an "i8** @llvm.swift.async.context.addr()" intrinsic providing front-ends access to this slot (and forcing its creation initialized to nullptr if necessary).
263 lines
8.8 KiB
C++
263 lines
8.8 KiB
C++
//===-- llvm/CodeGen/TargetCallingConv.h - Calling Convention ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines types for working with calling-convention information.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_TARGETCALLINGCONV_H
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#define LLVM_CODEGEN_TARGETCALLINGCONV_H
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/Alignment.h"
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#include "llvm/Support/MachineValueType.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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#include <climits>
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#include <cstdint>
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namespace llvm {
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namespace ISD {
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struct ArgFlagsTy {
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private:
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unsigned IsZExt : 1; ///< Zero extended
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unsigned IsSExt : 1; ///< Sign extended
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unsigned IsInReg : 1; ///< Passed in register
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unsigned IsSRet : 1; ///< Hidden struct-ret ptr
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unsigned IsByVal : 1; ///< Struct passed by value
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unsigned IsByRef : 1; ///< Passed in memory
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unsigned IsNest : 1; ///< Nested fn static chain
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unsigned IsReturned : 1; ///< Always returned
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unsigned IsSplit : 1;
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unsigned IsInAlloca : 1; ///< Passed with inalloca
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unsigned IsPreallocated : 1; ///< ByVal without the copy
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unsigned IsSplitEnd : 1; ///< Last part of a split
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unsigned IsSwiftSelf : 1; ///< Swift self parameter
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unsigned IsSwiftAsync : 1; ///< Swift async context parameter
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unsigned IsSwiftError : 1; ///< Swift error parameter
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unsigned IsCFGuardTarget : 1; ///< Control Flow Guard target
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unsigned IsHva : 1; ///< HVA field for
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unsigned IsHvaStart : 1; ///< HVA structure start
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unsigned IsSecArgPass : 1; ///< Second argument
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unsigned MemAlign : 4; ///< Log 2 of alignment when arg is passed in memory
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///< (including byval/byref)
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unsigned OrigAlign : 5; ///< Log 2 of original alignment
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unsigned IsInConsecutiveRegsLast : 1;
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unsigned IsInConsecutiveRegs : 1;
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unsigned IsCopyElisionCandidate : 1; ///< Argument copy elision candidate
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unsigned IsPointer : 1;
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unsigned ByValOrByRefSize; ///< Byval or byref struct size
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unsigned PointerAddrSpace; ///< Address space of pointer argument
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public:
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ArgFlagsTy()
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: IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsByRef(0),
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IsNest(0), IsReturned(0), IsSplit(0), IsInAlloca(0),
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IsPreallocated(0), IsSplitEnd(0), IsSwiftSelf(0), IsSwiftAsync(0),
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IsSwiftError(0), IsCFGuardTarget(0), IsHva(0), IsHvaStart(0),
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IsSecArgPass(0), MemAlign(0), OrigAlign(0),
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IsInConsecutiveRegsLast(0), IsInConsecutiveRegs(0),
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IsCopyElisionCandidate(0), IsPointer(0), ByValOrByRefSize(0),
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PointerAddrSpace(0) {
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static_assert(sizeof(*this) == 3 * sizeof(unsigned), "flags are too big");
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}
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bool isZExt() const { return IsZExt; }
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void setZExt() { IsZExt = 1; }
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bool isSExt() const { return IsSExt; }
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void setSExt() { IsSExt = 1; }
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bool isInReg() const { return IsInReg; }
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void setInReg() { IsInReg = 1; }
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bool isSRet() const { return IsSRet; }
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void setSRet() { IsSRet = 1; }
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bool isByVal() const { return IsByVal; }
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void setByVal() { IsByVal = 1; }
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bool isByRef() const { return IsByRef; }
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void setByRef() { IsByRef = 1; }
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bool isInAlloca() const { return IsInAlloca; }
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void setInAlloca() { IsInAlloca = 1; }
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bool isPreallocated() const { return IsPreallocated; }
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void setPreallocated() { IsPreallocated = 1; }
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bool isSwiftSelf() const { return IsSwiftSelf; }
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void setSwiftSelf() { IsSwiftSelf = 1; }
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bool isSwiftAsync() const { return IsSwiftAsync; }
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void setSwiftAsync() { IsSwiftAsync = 1; }
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bool isSwiftError() const { return IsSwiftError; }
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void setSwiftError() { IsSwiftError = 1; }
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bool isCFGuardTarget() const { return IsCFGuardTarget; }
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void setCFGuardTarget() { IsCFGuardTarget = 1; }
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bool isHva() const { return IsHva; }
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void setHva() { IsHva = 1; }
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bool isHvaStart() const { return IsHvaStart; }
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void setHvaStart() { IsHvaStart = 1; }
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bool isSecArgPass() const { return IsSecArgPass; }
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void setSecArgPass() { IsSecArgPass = 1; }
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bool isNest() const { return IsNest; }
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void setNest() { IsNest = 1; }
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bool isReturned() const { return IsReturned; }
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void setReturned(bool V = true) { IsReturned = V; }
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bool isInConsecutiveRegs() const { return IsInConsecutiveRegs; }
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void setInConsecutiveRegs(bool Flag = true) { IsInConsecutiveRegs = Flag; }
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bool isInConsecutiveRegsLast() const { return IsInConsecutiveRegsLast; }
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void setInConsecutiveRegsLast(bool Flag = true) {
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IsInConsecutiveRegsLast = Flag;
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}
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bool isSplit() const { return IsSplit; }
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void setSplit() { IsSplit = 1; }
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bool isSplitEnd() const { return IsSplitEnd; }
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void setSplitEnd() { IsSplitEnd = 1; }
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bool isCopyElisionCandidate() const { return IsCopyElisionCandidate; }
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void setCopyElisionCandidate() { IsCopyElisionCandidate = 1; }
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bool isPointer() const { return IsPointer; }
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void setPointer() { IsPointer = 1; }
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Align getNonZeroMemAlign() const {
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return decodeMaybeAlign(MemAlign).valueOrOne();
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}
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void setMemAlign(Align A) {
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MemAlign = encode(A);
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assert(getNonZeroMemAlign() == A && "bitfield overflow");
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}
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Align getNonZeroByValAlign() const {
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assert(isByVal());
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MaybeAlign A = decodeMaybeAlign(MemAlign);
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assert(A && "ByValAlign must be defined");
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return *A;
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}
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Align getNonZeroOrigAlign() const {
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return decodeMaybeAlign(OrigAlign).valueOrOne();
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}
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void setOrigAlign(Align A) {
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OrigAlign = encode(A);
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assert(getNonZeroOrigAlign() == A && "bitfield overflow");
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}
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unsigned getByValSize() const {
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assert(isByVal() && !isByRef());
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return ByValOrByRefSize;
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}
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void setByValSize(unsigned S) {
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assert(isByVal() && !isByRef());
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ByValOrByRefSize = S;
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}
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unsigned getByRefSize() const {
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assert(!isByVal() && isByRef());
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return ByValOrByRefSize;
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}
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void setByRefSize(unsigned S) {
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assert(!isByVal() && isByRef());
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ByValOrByRefSize = S;
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}
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unsigned getPointerAddrSpace() const { return PointerAddrSpace; }
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void setPointerAddrSpace(unsigned AS) { PointerAddrSpace = AS; }
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};
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/// InputArg - This struct carries flags and type information about a
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/// single incoming (formal) argument or incoming (from the perspective
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/// of the caller) return value virtual register.
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///
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struct InputArg {
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ArgFlagsTy Flags;
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MVT VT = MVT::Other;
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EVT ArgVT;
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bool Used = false;
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/// Index original Function's argument.
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unsigned OrigArgIndex;
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/// Sentinel value for implicit machine-level input arguments.
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static const unsigned NoArgIndex = UINT_MAX;
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/// Offset in bytes of current input value relative to the beginning of
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/// original argument. E.g. if argument was splitted into four 32 bit
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/// registers, we got 4 InputArgs with PartOffsets 0, 4, 8 and 12.
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unsigned PartOffset;
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InputArg() = default;
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InputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
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unsigned origIdx, unsigned partOffs)
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: Flags(flags), Used(used), OrigArgIndex(origIdx), PartOffset(partOffs) {
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VT = vt.getSimpleVT();
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ArgVT = argvt;
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}
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bool isOrigArg() const {
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return OrigArgIndex != NoArgIndex;
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}
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unsigned getOrigArgIndex() const {
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assert(OrigArgIndex != NoArgIndex && "Implicit machine-level argument");
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return OrigArgIndex;
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}
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};
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/// OutputArg - This struct carries flags and a value for a
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/// single outgoing (actual) argument or outgoing (from the perspective
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/// of the caller) return value virtual register.
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///
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struct OutputArg {
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ArgFlagsTy Flags;
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MVT VT;
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EVT ArgVT;
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/// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
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bool IsFixed = false;
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/// Index original Function's argument.
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unsigned OrigArgIndex;
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/// Offset in bytes of current output value relative to the beginning of
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/// original argument. E.g. if argument was splitted into four 32 bit
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/// registers, we got 4 OutputArgs with PartOffsets 0, 4, 8 and 12.
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unsigned PartOffset;
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OutputArg() = default;
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OutputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool isfixed,
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unsigned origIdx, unsigned partOffs)
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: Flags(flags), IsFixed(isfixed), OrigArgIndex(origIdx),
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PartOffset(partOffs) {
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VT = vt.getSimpleVT();
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ArgVT = argvt;
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}
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};
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} // end namespace ISD
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} // end namespace llvm
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#endif // LLVM_CODEGEN_TARGETCALLINGCONV_H
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