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e644e52d90
Intrinsics for the following instructions are added. The intrinsic name is "int_hexagon_<inst>[_128B]", e.g. int_hexagon_V6_vL32b_pred_ai for 64-byte version int_hexagon_V6_vL32b_pred_ai_128B for 128-byte version V6_vL32b_pred_ai if (Pv4) Vd32 = vmem(Rt32+#s4) V6_vL32b_pred_pi if (Pv4) Vd32 = vmem(Rx32++#s3) V6_vL32b_pred_ppu if (Pv4) Vd32 = vmem(Rx32++Mu2) V6_vL32b_npred_ai if (!Pv4) Vd32 = vmem(Rt32+#s4) V6_vL32b_npred_pi if (!Pv4) Vd32 = vmem(Rx32++#s3) V6_vL32b_npred_ppu if (!Pv4) Vd32 = vmem(Rx32++Mu2) V6_vL32b_nt_pred_ai if (Pv4) Vd32 = vmem(Rt32+#s4):nt V6_vL32b_nt_pred_pi if (Pv4) Vd32 = vmem(Rx32++#s3):nt V6_vL32b_nt_pred_ppu if (Pv4) Vd32 = vmem(Rx32++Mu2):nt V6_vL32b_nt_npred_ai if (!Pv4) Vd32 = vmem(Rt32+#s4):nt V6_vL32b_nt_npred_pi if (!Pv4) Vd32 = vmem(Rx32++#s3):nt V6_vL32b_nt_npred_ppu if (!Pv4) Vd32 = vmem(Rx32++Mu2):nt V6_vS32b_pred_ai if (Pv4) vmem(Rt32+#s4) = Vs32 V6_vS32b_pred_pi if (Pv4) vmem(Rx32++#s3) = Vs32 V6_vS32b_pred_ppu if (Pv4) vmem(Rx32++Mu2) = Vs32 V6_vS32b_npred_ai if (!Pv4) vmem(Rt32+#s4) = Vs32 V6_vS32b_npred_pi if (!Pv4) vmem(Rx32++#s3) = Vs32 V6_vS32b_npred_ppu if (!Pv4) vmem(Rx32++Mu2) = Vs32 V6_vS32Ub_pred_ai if (Pv4) vmemu(Rt32+#s4) = Vs32 V6_vS32Ub_pred_pi if (Pv4) vmemu(Rx32++#s3) = Vs32 V6_vS32Ub_pred_ppu if (Pv4) vmemu(Rx32++Mu2) = Vs32 V6_vS32Ub_npred_ai if (!Pv4) vmemu(Rt32+#s4) = Vs32 V6_vS32Ub_npred_pi if (!Pv4) vmemu(Rx32++#s3) = Vs32 V6_vS32Ub_npred_ppu if (!Pv4) vmemu(Rx32++Mu2) = Vs32 V6_vS32b_nt_pred_ai if (Pv4) vmem(Rt32+#s4):nt = Vs32 V6_vS32b_nt_pred_pi if (Pv4) vmem(Rx32++#s3):nt = Vs32 V6_vS32b_nt_pred_ppu if (Pv4) vmem(Rx32++Mu2):nt = Vs32 V6_vS32b_nt_npred_ai if (!Pv4) vmem(Rt32+#s4):nt = Vs32 V6_vS32b_nt_npred_pi if (!Pv4) vmem(Rx32++#s3):nt = Vs32 V6_vS32b_nt_npred_ppu if (!Pv4) vmem(Rx32++Mu2):nt = Vs32
408 lines
18 KiB
TableGen
408 lines
18 KiB
TableGen
//===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the Hexagon-specific intrinsics.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Definitions for all Hexagon intrinsics.
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//
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// All Hexagon intrinsics start with "llvm.hexagon.".
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let TargetPrefix = "hexagon" in {
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/// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics.
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class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
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list<LLVMType> param_types,
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list<IntrinsicProperty> properties>
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: GCCBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
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Intrinsic<ret_types, param_types, properties>;
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/// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon
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/// intrinsics.
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class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types,
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list<LLVMType> param_types,
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list<IntrinsicProperty> properties>
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: Intrinsic<ret_types, param_types, properties>;
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}
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class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix>
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: Hexagon_Intrinsic<GCCIntSuffix,
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[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
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llvm_i32_ty],
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[IntrArgMemOnly]>;
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class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix>
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: Hexagon_Intrinsic<GCCIntSuffix,
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[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
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llvm_i32_ty],
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[IntrWriteMem]>;
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class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix>
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: Hexagon_Intrinsic<GCCIntSuffix,
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[llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
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llvm_i32_ty],
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[IntrWriteMem]>;
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class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix>
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: Hexagon_Intrinsic<GCCIntSuffix,
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[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
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llvm_i32_ty, llvm_i32_ty],
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[IntrArgMemOnly, ImmArg<ArgIndex<3>>]>;
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class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix>
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: Hexagon_Intrinsic<GCCIntSuffix,
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[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty],
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[IntrWriteMem, ImmArg<ArgIndex<3>>]>;
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class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix>
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: Hexagon_Intrinsic<GCCIntSuffix,
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[llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
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llvm_i32_ty, llvm_i32_ty],
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[IntrWriteMem, ImmArg<ArgIndex<3>>]>;
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//
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// BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4)
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//
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def int_hexagon_circ_ldd :
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Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">;
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//
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// BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4)
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//
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def int_hexagon_circ_ldw :
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Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">;
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//
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// BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4)
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//
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def int_hexagon_circ_ldh :
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Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">;
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//
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// BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4)
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//
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def int_hexagon_circ_lduh :
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Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">;
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//
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// BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4)
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//
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def int_hexagon_circ_ldb :
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Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">;
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//
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// BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4)
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//
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def int_hexagon_circ_ldub :
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Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">;
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//
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// BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4)
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//
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def int_hexagon_circ_std :
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Hexagon_mem_memdisisi_Intrinsic<"circ_std">;
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//
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// BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4)
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//
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def int_hexagon_circ_stw :
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Hexagon_mem_memsisisi_Intrinsic<"circ_stw">;
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//
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// BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4)
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//
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def int_hexagon_circ_sth :
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Hexagon_mem_memsisisi_Intrinsic<"circ_sth">;
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//
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// BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4)
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//
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def int_hexagon_circ_sthhi :
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Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">;
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//
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// BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4)
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//
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def int_hexagon_circ_stb :
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Hexagon_mem_memsisisi_Intrinsic<"circ_stb">;
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def int_hexagon_prefetch :
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Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>;
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def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>;
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def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>;
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// Mark locked loads as read/write to prevent any accidental reordering.
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def int_hexagon_L2_loadw_locked :
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Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty],
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[IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
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def int_hexagon_L4_loadd_locked :
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Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty],
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[IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
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def int_hexagon_S2_storew_locked :
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Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty],
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[llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
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def int_hexagon_S4_stored_locked :
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Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty],
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[llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
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def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy",
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[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
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[IntrArgMemOnly, NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>, WriteOnly<ArgIndex<0>>, ReadOnly<ArgIndex<1>>]>;
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def int_hexagon_vmemset : Hexagon_Intrinsic<"hexagon_vmemset",
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[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>;
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multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> {
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def NAME#_pci : Hexagon_NonGCC_Intrinsic<
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[ElTy, llvm_ptr_ty],
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[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty],
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[IntrArgMemOnly, NoCapture<ArgIndex<3>>]>;
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def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
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[ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty],
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[IntrArgMemOnly, NoCapture<ArgIndex<2>>]>;
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}
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defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>;
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multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> {
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def NAME#_pci : Hexagon_NonGCC_Intrinsic<
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[llvm_ptr_ty],
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[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
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[IntrArgMemOnly, NoCapture<ArgIndex<4>>]>;
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def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
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[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
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[IntrArgMemOnly, NoCapture<ArgIndex<3>>]>;
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}
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defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
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defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>;
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// The front-end emits the intrinsic call with only two arguments. The third
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// argument from the builtin is already used by front-end to write to memory
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// by generating a store.
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class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy>
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: Hexagon_NonGCC_Intrinsic<
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[ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty],
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[IntrReadMem]>;
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def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
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def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
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def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
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def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
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def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
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def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>;
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def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">;
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def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">;
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def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">;
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def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">;
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def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">;
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// tag : V6_vrmpybub_rtt
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class Hexagon_v32i32_v16i32i64_rtt_Intrinsic<string GCCIntSuffix>
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: Hexagon_Intrinsic<GCCIntSuffix,
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[llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
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[IntrNoMem]>;
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// tag : V6_vrmpybub_rtt_128B
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class Hexagon_v64i32_v32i32i64_rtt_Intrinsic<string GCCIntSuffix>
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: Hexagon_Intrinsic<GCCIntSuffix,
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[llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
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[IntrNoMem]>;
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// tag : V6_vrmpybub_rtt_acc
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class Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<string GCCIntSuffix>
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: Hexagon_Intrinsic<GCCIntSuffix,
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[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],
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[IntrNoMem]>;
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// tag : V6_vrmpybub_rtt_acc_128B
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class Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<string GCCIntSuffix>
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: Hexagon_Intrinsic<GCCIntSuffix,
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[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],
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[IntrNoMem]>;
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def int_hexagon_V6_vrmpybub_rtt :
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Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">;
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def int_hexagon_V6_vrmpybub_rtt_128B :
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Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">;
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def int_hexagon_V6_vrmpybub_rtt_acc :
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Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">;
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def int_hexagon_V6_vrmpybub_rtt_acc_128B :
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Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">;
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def int_hexagon_V6_vrmpyub_rtt :
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Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">;
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def int_hexagon_V6_vrmpyub_rtt_128B :
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Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">;
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def int_hexagon_V6_vrmpyub_rtt_acc :
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Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">;
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def int_hexagon_V6_vrmpyub_rtt_acc_128B :
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Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">;
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// HVX conditional loads/stores
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class Hexagon_pred_vload_imm<LLVMType ValTy>
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: Hexagon_NonGCC_Intrinsic<
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[ValTy],
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[llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty],
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[IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>,
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ImmArg<ArgIndex<2>>]>;
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class Hexagon_pred_vload_imm_64B: Hexagon_pred_vload_imm<llvm_v16i32_ty>;
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class Hexagon_pred_vload_imm_128B: Hexagon_pred_vload_imm<llvm_v32i32_ty>;
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def int_hexagon_V6_vL32b_pred_ai: Hexagon_pred_vload_imm_64B;
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def int_hexagon_V6_vL32b_npred_ai: Hexagon_pred_vload_imm_64B;
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def int_hexagon_V6_vL32b_nt_pred_ai: Hexagon_pred_vload_imm_64B;
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def int_hexagon_V6_vL32b_nt_npred_ai: Hexagon_pred_vload_imm_64B;
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def int_hexagon_V6_vL32b_pred_ai_128B: Hexagon_pred_vload_imm_128B;
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def int_hexagon_V6_vL32b_npred_ai_128B: Hexagon_pred_vload_imm_128B;
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def int_hexagon_V6_vL32b_nt_pred_ai_128B: Hexagon_pred_vload_imm_128B;
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def int_hexagon_V6_vL32b_nt_npred_ai_128B: Hexagon_pred_vload_imm_128B;
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class Hexagom_pred_vload_upd<LLVMType ValTy, bit TakesImm>
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: Hexagon_NonGCC_Intrinsic<
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[ValTy, LLVMPointerType<ValTy>],
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[llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty],
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!if(TakesImm,
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[IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>,
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ImmArg<ArgIndex<2>>],
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[IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>])>;
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class Hexagom_pred_vload_upd_64B<bit TakesImm>
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: Hexagom_pred_vload_upd<llvm_v16i32_ty, TakesImm>;
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class Hexagom_pred_vload_upd_128B<bit TakesImm>
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: Hexagom_pred_vload_upd<llvm_v32i32_ty, TakesImm>;
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def int_hexagon_V6_vL32b_pred_pi: Hexagom_pred_vload_upd_64B<1>;
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def int_hexagon_V6_vL32b_npred_pi: Hexagom_pred_vload_upd_64B<1>;
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def int_hexagon_V6_vL32b_nt_pred_pi: Hexagom_pred_vload_upd_64B<1>;
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def int_hexagon_V6_vL32b_nt_npred_pi: Hexagom_pred_vload_upd_64B<1>;
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def int_hexagon_V6_vL32b_pred_pi_128B: Hexagom_pred_vload_upd_128B<1>;
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def int_hexagon_V6_vL32b_npred_pi_128B: Hexagom_pred_vload_upd_128B<1>;
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def int_hexagon_V6_vL32b_nt_pred_pi_128B: Hexagom_pred_vload_upd_128B<1>;
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def int_hexagon_V6_vL32b_nt_npred_pi_128B: Hexagom_pred_vload_upd_128B<1>;
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def int_hexagon_V6_vL32b_pred_ppu: Hexagom_pred_vload_upd_64B<0>;
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def int_hexagon_V6_vL32b_npred_ppu: Hexagom_pred_vload_upd_64B<0>;
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def int_hexagon_V6_vL32b_nt_pred_ppu: Hexagom_pred_vload_upd_64B<0>;
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def int_hexagon_V6_vL32b_nt_npred_ppu: Hexagom_pred_vload_upd_64B<0>;
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def int_hexagon_V6_vL32b_pred_ppu_128B: Hexagom_pred_vload_upd_128B<0>;
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def int_hexagon_V6_vL32b_npred_ppu_128B: Hexagom_pred_vload_upd_128B<0>;
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def int_hexagon_V6_vL32b_nt_pred_ppu_128B: Hexagom_pred_vload_upd_128B<0>;
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def int_hexagon_V6_vL32b_nt_npred_ppu_128B: Hexagom_pred_vload_upd_128B<0>;
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class Hexagon_pred_vstore_imm<LLVMType ValTy>
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: Hexagon_NonGCC_Intrinsic<
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[],
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[llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty, ValTy],
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[IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>,
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ImmArg<ArgIndex<2>>]>;
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class Hexagon_pred_vstore_imm_64B: Hexagon_pred_vstore_imm<llvm_v16i32_ty>;
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class Hexagon_pred_vstore_imm_128B: Hexagon_pred_vstore_imm<llvm_v32i32_ty>;
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def int_hexagon_V6_vS32b_pred_ai: Hexagon_pred_vstore_imm_64B;
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def int_hexagon_V6_vS32b_npred_ai: Hexagon_pred_vstore_imm_64B;
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def int_hexagon_V6_vS32Ub_pred_ai: Hexagon_pred_vstore_imm_64B;
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def int_hexagon_V6_vS32Ub_npred_ai: Hexagon_pred_vstore_imm_64B;
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def int_hexagon_V6_vS32b_nt_pred_ai: Hexagon_pred_vstore_imm_64B;
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def int_hexagon_V6_vS32b_nt_npred_ai: Hexagon_pred_vstore_imm_64B;
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def int_hexagon_V6_vS32b_pred_ai_128B: Hexagon_pred_vstore_imm_128B;
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def int_hexagon_V6_vS32b_npred_ai_128B: Hexagon_pred_vstore_imm_128B;
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def int_hexagon_V6_vS32Ub_pred_ai_128B: Hexagon_pred_vstore_imm_128B;
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def int_hexagon_V6_vS32Ub_npred_ai_128B: Hexagon_pred_vstore_imm_128B;
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def int_hexagon_V6_vS32b_nt_pred_ai_128B: Hexagon_pred_vstore_imm_128B;
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def int_hexagon_V6_vS32b_nt_npred_ai_128B: Hexagon_pred_vstore_imm_128B;
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class Hexagon_pred_vstore_upd<LLVMType ValTy, bit TakesImm>
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: Hexagon_NonGCC_Intrinsic<
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[LLVMPointerType<ValTy>],
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[llvm_i1_ty, LLVMPointerType<ValTy>, llvm_i32_ty, ValTy],
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!if(TakesImm,
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[IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>,
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ImmArg<ArgIndex<2>>],
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[IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>])>;
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class Hexagon_pred_vstore_upd_64B<bit TakesImm>
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: Hexagon_pred_vstore_upd<llvm_v16i32_ty, TakesImm>;
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class Hexagon_pred_vstore_upd_128B<bit TakesImm>
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: Hexagon_pred_vstore_upd<llvm_v32i32_ty, TakesImm>;
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def int_hexagon_V6_vS32b_pred_pi: Hexagon_pred_vstore_upd_64B<1>;
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def int_hexagon_V6_vS32b_npred_pi: Hexagon_pred_vstore_upd_64B<1>;
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def int_hexagon_V6_vS32Ub_pred_pi: Hexagon_pred_vstore_upd_64B<1>;
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def int_hexagon_V6_vS32Ub_npred_pi: Hexagon_pred_vstore_upd_64B<1>;
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def int_hexagon_V6_vS32b_nt_pred_pi: Hexagon_pred_vstore_upd_64B<1>;
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def int_hexagon_V6_vS32b_nt_npred_pi: Hexagon_pred_vstore_upd_64B<1>;
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def int_hexagon_V6_vS32b_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
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def int_hexagon_V6_vS32b_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
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def int_hexagon_V6_vS32Ub_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
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def int_hexagon_V6_vS32Ub_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
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def int_hexagon_V6_vS32b_nt_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
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def int_hexagon_V6_vS32b_nt_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>;
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def int_hexagon_V6_vS32b_pred_ppu: Hexagon_pred_vstore_upd_64B<0>;
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def int_hexagon_V6_vS32b_npred_ppu: Hexagon_pred_vstore_upd_64B<0>;
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def int_hexagon_V6_vS32Ub_pred_ppu: Hexagon_pred_vstore_upd_64B<0>;
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def int_hexagon_V6_vS32Ub_npred_ppu: Hexagon_pred_vstore_upd_64B<0>;
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def int_hexagon_V6_vS32b_nt_pred_ppu: Hexagon_pred_vstore_upd_64B<0>;
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def int_hexagon_V6_vS32b_nt_npred_ppu: Hexagon_pred_vstore_upd_64B<0>;
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def int_hexagon_V6_vS32b_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
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def int_hexagon_V6_vS32b_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
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def int_hexagon_V6_vS32Ub_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
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def int_hexagon_V6_vS32Ub_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
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def int_hexagon_V6_vS32b_nt_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
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def int_hexagon_V6_vS32b_nt_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>;
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// HVX Vector predicate casts.
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|
// These intrinsics do not emit (nor do they correspond to) any instructions,
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|
// they are no-ops.
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|
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|
def int_hexagon_V6_pred_typecast :
|
|
Hexagon_NonGCC_Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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|
|
|
def int_hexagon_V6_pred_typecast_128B :
|
|
Hexagon_NonGCC_Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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|
|
|
// Masked vector stores
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|
//
|
|
// These are all deprecated, the intrinsics matching instruction names
|
|
// should be used instead, e.g. int_hexagon_V6_vS32b_qpred_ai, etc.
|
|
|
|
class Hexagon_custom_vms_Intrinsic
|
|
: Hexagon_NonGCC_Intrinsic<
|
|
[], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty], [IntrWriteMem]>;
|
|
|
|
class Hexagon_custom_vms_Intrinsic_128B
|
|
: Hexagon_NonGCC_Intrinsic<
|
|
[], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty], [IntrWriteMem]>;
|
|
|
|
def int_hexagon_V6_vmaskedstoreq: Hexagon_custom_vms_Intrinsic;
|
|
def int_hexagon_V6_vmaskedstorenq: Hexagon_custom_vms_Intrinsic;
|
|
def int_hexagon_V6_vmaskedstorentq: Hexagon_custom_vms_Intrinsic;
|
|
def int_hexagon_V6_vmaskedstorentnq: Hexagon_custom_vms_Intrinsic;
|
|
|
|
def int_hexagon_V6_vmaskedstoreq_128B: Hexagon_custom_vms_Intrinsic_128B;
|
|
def int_hexagon_V6_vmaskedstorenq_128B: Hexagon_custom_vms_Intrinsic_128B;
|
|
def int_hexagon_V6_vmaskedstorentq_128B: Hexagon_custom_vms_Intrinsic_128B;
|
|
def int_hexagon_V6_vmaskedstorentnq_128B: Hexagon_custom_vms_Intrinsic_128B;
|
|
|
|
include "llvm/IR/IntrinsicsHexagonDep.td"
|