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282 lines
8.8 KiB
C++
282 lines
8.8 KiB
C++
//===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise ARM hardware features
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// such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_ARMTARGETPARSER_H
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#define LLVM_SUPPORT_ARMTARGETPARSER_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/ARMBuildAttributes.h"
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#include <vector>
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namespace llvm {
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class Triple;
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namespace ARM {
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// Arch extension modifiers for CPUs.
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// Note that this is not the same as the AArch64 list
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enum ArchExtKind : uint64_t {
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AEK_INVALID = 0,
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AEK_NONE = 1,
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AEK_CRC = 1 << 1,
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AEK_CRYPTO = 1 << 2,
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AEK_FP = 1 << 3,
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AEK_HWDIVTHUMB = 1 << 4,
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AEK_HWDIVARM = 1 << 5,
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AEK_MP = 1 << 6,
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AEK_SIMD = 1 << 7,
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AEK_SEC = 1 << 8,
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AEK_VIRT = 1 << 9,
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AEK_DSP = 1 << 10,
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AEK_FP16 = 1 << 11,
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AEK_RAS = 1 << 12,
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AEK_DOTPROD = 1 << 13,
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AEK_SHA2 = 1 << 14,
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AEK_AES = 1 << 15,
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AEK_FP16FML = 1 << 16,
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AEK_SB = 1 << 17,
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AEK_FP_DP = 1 << 18,
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AEK_LOB = 1 << 19,
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AEK_BF16 = 1 << 20,
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AEK_I8MM = 1 << 21,
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AEK_CDECP0 = 1 << 22,
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AEK_CDECP1 = 1 << 23,
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AEK_CDECP2 = 1 << 24,
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AEK_CDECP3 = 1 << 25,
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AEK_CDECP4 = 1 << 26,
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AEK_CDECP5 = 1 << 27,
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AEK_CDECP6 = 1 << 28,
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AEK_CDECP7 = 1 << 29,
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// Unsupported extensions.
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AEK_OS = 1ULL << 59,
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AEK_IWMMXT = 1ULL << 60,
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AEK_IWMMXT2 = 1ULL << 61,
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AEK_MAVERICK = 1ULL << 62,
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AEK_XSCALE = 1ULL << 63,
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};
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// List of Arch Extension names.
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// FIXME: TableGen this.
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struct ExtName {
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const char *NameCStr;
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size_t NameLength;
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uint64_t ID;
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const char *Feature;
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const char *NegFeature;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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};
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const ExtName ARCHExtNames[] = {
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#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \
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{NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE},
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#include "ARMTargetParser.def"
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};
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// List of HWDiv names (use getHWDivSynonym) and which architectural
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// features they correspond to (use getHWDivFeatures).
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// FIXME: TableGen this.
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const struct {
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const char *NameCStr;
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size_t NameLength;
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uint64_t ID;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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} HWDivNames[] = {
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#define ARM_HW_DIV_NAME(NAME, ID) {NAME, sizeof(NAME) - 1, ID},
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#include "ARMTargetParser.def"
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};
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// Arch names.
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enum class ArchKind {
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#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
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#include "ARMTargetParser.def"
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};
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// List of CPU names and their arches.
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// The same CPU can have multiple arches and can be default on multiple arches.
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// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
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// When this becomes table-generated, we'd probably need two tables.
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// FIXME: TableGen this.
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template <typename T> struct CpuNames {
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const char *NameCStr;
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size_t NameLength;
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T ArchID;
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bool Default; // is $Name the default CPU for $ArchID ?
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uint64_t DefaultExtensions;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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};
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const CpuNames<ArchKind> CPUNames[] = {
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#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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{NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
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#include "ARMTargetParser.def"
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};
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// FPU names.
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enum FPUKind {
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#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
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#include "ARMTargetParser.def"
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FK_LAST
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};
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// FPU Version
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enum class FPUVersion {
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NONE,
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VFPV2,
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VFPV3,
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VFPV3_FP16,
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VFPV4,
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VFPV5,
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VFPV5_FULLFP16,
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};
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// An FPU name restricts the FPU in one of three ways:
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enum class FPURestriction {
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None = 0, ///< No restriction
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D16, ///< Only 16 D registers
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SP_D16 ///< Only single-precision instructions, with 16 D registers
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};
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// An FPU name implies one of three levels of Neon support:
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enum class NeonSupportLevel {
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None = 0, ///< No Neon
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Neon, ///< Neon
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Crypto ///< Neon with Crypto
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};
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// ISA kinds.
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enum class ISAKind { INVALID = 0, ARM, THUMB, AARCH64 };
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// Endianness
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// FIXME: BE8 vs. BE32?
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enum class EndianKind { INVALID = 0, LITTLE, BIG };
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// v6/v7/v8 Profile
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enum class ProfileKind { INVALID = 0, A, R, M };
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// List of canonical FPU names (use getFPUSynonym) and which architectural
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// features they correspond to (use getFPUFeatures).
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// FIXME: TableGen this.
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// The entries must appear in the order listed in ARM::FPUKind for correct
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// indexing
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struct FPUName {
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const char *NameCStr;
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size_t NameLength;
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FPUKind ID;
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FPUVersion FPUVer;
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NeonSupportLevel NeonSupport;
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FPURestriction Restriction;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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};
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static const FPUName FPUNames[] = {
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#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \
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{NAME, sizeof(NAME) - 1, KIND, VERSION, NEON_SUPPORT, RESTRICTION},
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#include "llvm/Support/ARMTargetParser.def"
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};
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// List of canonical arch names (use getArchSynonym).
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// This table also provides the build attribute fields for CPU arch
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// and Arch ID, according to the Addenda to the ARM ABI, chapters
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// 2.4 and 2.3.5.2 respectively.
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// FIXME: SubArch values were simplified to fit into the expectations
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// of the triples and are not conforming with their official names.
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// Check to see if the expectation should be changed.
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// FIXME: TableGen this.
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template <typename T> struct ArchNames {
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const char *NameCStr;
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size_t NameLength;
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const char *CPUAttrCStr;
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size_t CPUAttrLength;
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const char *SubArchCStr;
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size_t SubArchLength;
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unsigned DefaultFPU;
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uint64_t ArchBaseExtensions;
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T ID;
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ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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// CPU class in build attributes.
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StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); }
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// Sub-Arch name.
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StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); }
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};
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static const ArchNames<ArchKind> ARCHNames[] = {
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#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, \
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ARCH_BASE_EXT) \
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{NAME, sizeof(NAME) - 1, \
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CPU_ATTR, sizeof(CPU_ATTR) - 1, \
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SUB_ARCH, sizeof(SUB_ARCH) - 1, \
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ARCH_FPU, ARCH_BASE_EXT, \
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ArchKind::ID, ARCH_ATTR},
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#include "llvm/Support/ARMTargetParser.def"
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};
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// Information by ID
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StringRef getFPUName(unsigned FPUKind);
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FPUVersion getFPUVersion(unsigned FPUKind);
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NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);
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FPURestriction getFPURestriction(unsigned FPUKind);
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// FIXME: These should be moved to TargetTuple once it exists
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bool getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features);
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bool getHWDivFeatures(uint64_t HWDivKind, std::vector<StringRef> &Features);
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bool getExtensionFeatures(uint64_t Extensions,
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std::vector<StringRef> &Features);
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StringRef getArchName(ArchKind AK);
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unsigned getArchAttr(ArchKind AK);
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StringRef getCPUAttr(ArchKind AK);
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StringRef getSubArch(ArchKind AK);
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StringRef getArchExtName(uint64_t ArchExtKind);
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StringRef getArchExtFeature(StringRef ArchExt);
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bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK, StringRef ArchExt,
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std::vector<StringRef> &Features,
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unsigned &ArgFPUKind);
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// Information by Name
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unsigned getDefaultFPU(StringRef CPU, ArchKind AK);
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uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK);
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StringRef getDefaultCPU(StringRef Arch);
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StringRef getCanonicalArchName(StringRef Arch);
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StringRef getFPUSynonym(StringRef FPU);
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StringRef getArchSynonym(StringRef Arch);
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// Parser
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uint64_t parseHWDiv(StringRef HWDiv);
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unsigned parseFPU(StringRef FPU);
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ArchKind parseArch(StringRef Arch);
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uint64_t parseArchExt(StringRef ArchExt);
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ArchKind parseCPUArch(StringRef CPU);
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ISAKind parseArchISA(StringRef Arch);
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EndianKind parseArchEndian(StringRef Arch);
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ProfileKind parseArchProfile(StringRef Arch);
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unsigned parseArchVersion(StringRef Arch);
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
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StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
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} // namespace ARM
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} // namespace llvm
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#endif
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