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6634a71bd1
We see some shifts of zero emitted during legalization. Differential Revision: https://reviews.llvm.org/D106816
218 lines
9.1 KiB
TableGen
218 lines
9.1 KiB
TableGen
//=- AArch64.td - Define AArch64 Combine Rules ---------------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/GlobalISel/Combine.td"
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def fconstant_to_constant : GICombineRule<
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(defs root:$root),
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(match (wip_match_opcode G_FCONSTANT):$root,
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[{ return matchFConstantToConstant(*${root}, MRI); }]),
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(apply [{ applyFConstantToConstant(*${root}); }])>;
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def icmp_redundant_trunc_matchdata : GIDefMatchData<"Register">;
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def icmp_redundant_trunc : GICombineRule<
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(defs root:$root, icmp_redundant_trunc_matchdata:$matchinfo),
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(match (wip_match_opcode G_ICMP):$root,
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[{ return matchICmpRedundantTrunc(*${root}, MRI, Helper.getKnownBits(), ${matchinfo}); }]),
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(apply [{ applyICmpRedundantTrunc(*${root}, MRI, B, Observer, ${matchinfo}); }])>;
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// AArch64-specific offset folding for G_GLOBAL_VALUE.
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def fold_global_offset_matchdata : GIDefMatchData<"std::pair<uint64_t, uint64_t>">;
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def fold_global_offset : GICombineRule<
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(defs root:$root, fold_global_offset_matchdata:$matchinfo),
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(match (wip_match_opcode G_GLOBAL_VALUE):$root,
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[{ return matchFoldGlobalOffset(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ return applyFoldGlobalOffset(*${root}, MRI, B, Observer, ${matchinfo});}])
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>;
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def AArch64PreLegalizerCombinerHelper: GICombinerHelper<
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"AArch64GenPreLegalizerCombinerHelper", [all_combines,
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fconstant_to_constant,
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icmp_redundant_trunc,
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fold_global_offset]> {
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let DisableRuleOption = "aarch64prelegalizercombiner-disable-rule";
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let StateClass = "AArch64PreLegalizerCombinerHelperState";
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let AdditionalArguments = [];
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}
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def AArch64O0PreLegalizerCombinerHelper: GICombinerHelper<
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"AArch64GenO0PreLegalizerCombinerHelper", [optnone_combines]> {
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let DisableRuleOption = "aarch64O0prelegalizercombiner-disable-rule";
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let StateClass = "AArch64O0PreLegalizerCombinerHelperState";
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let AdditionalArguments = [];
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}
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// Matchdata for combines which replace a G_SHUFFLE_VECTOR with a
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// target-specific opcode.
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def shuffle_matchdata : GIDefMatchData<"ShuffleVectorPseudo">;
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def rev : GICombineRule<
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def zip : GICombineRule<
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def uzp : GICombineRule<
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def dup: GICombineRule <
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def trn : GICombineRule<
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchTRN(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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def ext: GICombineRule <
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchEXT(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyEXT(*${root}, ${matchinfo}); }])
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>;
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def shuf_to_ins_matchdata : GIDefMatchData<"std::tuple<Register, int, Register, int>">;
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def shuf_to_ins: GICombineRule <
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(defs root:$root, shuf_to_ins_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchINS(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ return applyINS(*${root}, MRI, B, ${matchinfo}); }])
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>;
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def vashr_vlshr_imm_matchdata : GIDefMatchData<"int64_t">;
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def vashr_vlshr_imm : GICombineRule<
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(defs root:$root, vashr_vlshr_imm_matchdata:$matchinfo),
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(match (wip_match_opcode G_ASHR, G_LSHR):$root,
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[{ return matchVAshrLshrImm(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyVAshrLshrImm(*${root}, MRI, ${matchinfo}); }])
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>;
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def form_duplane_matchdata :
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GIDefMatchData<"std::pair<unsigned, int>">;
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def form_duplane : GICombineRule <
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(defs root:$root, form_duplane_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchDupLane(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyDupLane(*${root}, MRI, B, ${matchinfo}); }])
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>;
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def shuffle_vector_lowering : GICombineGroup<[dup, rev, ext, zip, uzp, trn,
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form_duplane,
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shuf_to_ins]>;
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def adjust_icmp_imm_matchdata :
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GIDefMatchData<"std::pair<uint64_t, CmpInst::Predicate>">;
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def adjust_icmp_imm : GICombineRule <
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(defs root:$root, adjust_icmp_imm_matchdata:$matchinfo),
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(match (wip_match_opcode G_ICMP):$root,
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[{ return matchAdjustICmpImmAndPred(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyAdjustICmpImmAndPred(*${root}, ${matchinfo}, B, Observer); }])
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>;
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def swap_icmp_operands : GICombineRule <
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(defs root:$root),
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(match (wip_match_opcode G_ICMP):$root,
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[{ return trySwapICmpOperands(*${root}, MRI); }]),
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(apply [{ applySwapICmpOperands(*${root}, Observer); }])
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>;
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def icmp_lowering : GICombineGroup<[adjust_icmp_imm, swap_icmp_operands]>;
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def extractvecelt_pairwise_add_matchdata : GIDefMatchData<"std::tuple<unsigned, LLT, Register>">;
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def extractvecelt_pairwise_add : GICombineRule<
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(defs root:$root, extractvecelt_pairwise_add_matchdata:$matchinfo),
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(match (wip_match_opcode G_EXTRACT_VECTOR_ELT):$root,
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[{ return matchExtractVecEltPairwiseAdd(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyExtractVecEltPairwiseAdd(*${root}, MRI, B, ${matchinfo}); }])
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>;
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def mul_const_matchdata : GIDefMatchData<"std::function<void(MachineIRBuilder&, Register)>">;
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def mul_const : GICombineRule<
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(defs root:$root, mul_const_matchdata:$matchinfo),
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(match (wip_match_opcode G_MUL):$root,
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[{ return matchAArch64MulConstCombine(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyAArch64MulConstCombine(*${root}, MRI, B, ${matchinfo}); }])
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>;
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def build_vector_to_dup : GICombineRule<
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(defs root:$root),
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(match (wip_match_opcode G_BUILD_VECTOR):$root,
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[{ return matchBuildVectorToDup(*${root}, MRI); }]),
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(apply [{ return applyBuildVectorToDup(*${root}, MRI, B); }])
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>;
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def build_vector_lowering : GICombineGroup<[build_vector_to_dup]>;
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def lower_vector_fcmp : GICombineRule<
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(defs root:$root),
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(match (wip_match_opcode G_FCMP):$root,
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[{ return lowerVectorFCMP(*${root}, MRI, B); }]),
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(apply [{}])>;
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def form_truncstore_matchdata : GIDefMatchData<"Register">;
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def form_truncstore : GICombineRule<
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(defs root:$root, form_truncstore_matchdata:$matchinfo),
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(match (wip_match_opcode G_STORE):$root,
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[{ return matchFormTruncstore(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyFormTruncstore(*${root}, MRI, B, Observer, ${matchinfo}); }])
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>;
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def fold_merge_to_zext : GICombineRule<
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(defs root:$d),
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(match (wip_match_opcode G_MERGE_VALUES):$d,
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[{ return matchFoldMergeToZext(*${d}, MRI); }]),
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(apply [{ applyFoldMergeToZext(*${d}, MRI, B, Observer); }])
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>;
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// Post-legalization combines which should happen at all optimization levels.
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// (E.g. ones that facilitate matching for the selector) For example, matching
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// pseudos.
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def AArch64PostLegalizerLoweringHelper
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: GICombinerHelper<"AArch64GenPostLegalizerLoweringHelper",
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[shuffle_vector_lowering, vashr_vlshr_imm,
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icmp_lowering, build_vector_lowering,
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lower_vector_fcmp, form_truncstore]> {
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let DisableRuleOption = "aarch64postlegalizerlowering-disable-rule";
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}
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// Post-legalization combines which are primarily optimizations.
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def AArch64PostLegalizerCombinerHelper
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: GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
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[copy_prop, erase_undef_store, combines_for_extload,
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sext_trunc_sextload,
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hoist_logic_op_with_same_opcode_hands,
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redundant_and, xor_of_and_with_same_reg,
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extractvecelt_pairwise_add, redundant_or,
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mul_const, redundant_sext_inreg,
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form_bitfield_extract, rotate_out_of_range,
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icmp_to_true_false_known_bits, merge_unmerge,
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select_combines, fold_merge_to_zext,
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constant_fold, identity_combines]> {
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let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
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}
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