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302 lines
10 KiB
C++
302 lines
10 KiB
C++
//=== lib/CodeGen/GlobalISel/AMDGPUPreLegalizerCombiner.cpp ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// before the legalizer.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPULegalizerInfo.h"
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Target/TargetMachine.h"
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#define DEBUG_TYPE "amdgpu-prelegalizer-combiner"
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using namespace llvm;
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using namespace MIPatternMatch;
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class AMDGPUPreLegalizerCombinerHelper {
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protected:
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MachineIRBuilder &B;
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MachineFunction &MF;
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MachineRegisterInfo &MRI;
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CombinerHelper &Helper;
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public:
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AMDGPUPreLegalizerCombinerHelper(MachineIRBuilder &B, CombinerHelper &Helper)
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: B(B), MF(B.getMF()), MRI(*B.getMRI()), Helper(Helper){};
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struct ClampI64ToI16MatchInfo {
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int64_t Cmp1 = 0;
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int64_t Cmp2 = 0;
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Register Origin;
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};
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bool matchClampI64ToI16(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineFunction &MF,
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ClampI64ToI16MatchInfo &MatchInfo);
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void applyClampI64ToI16(MachineInstr &MI,
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const ClampI64ToI16MatchInfo &MatchInfo);
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};
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bool AMDGPUPreLegalizerCombinerHelper::matchClampI64ToI16(
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MachineInstr &MI, MachineRegisterInfo &MRI, MachineFunction &MF,
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ClampI64ToI16MatchInfo &MatchInfo) {
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assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Invalid instruction!");
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// Try to find a pattern where an i64 value should get clamped to short.
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const LLT SrcType = MRI.getType(MI.getOperand(1).getReg());
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if (SrcType != LLT::scalar(64))
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return false;
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const LLT DstType = MRI.getType(MI.getOperand(0).getReg());
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if (DstType != LLT::scalar(16))
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return false;
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Register Base;
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auto IsApplicableForCombine = [&MatchInfo]() -> bool {
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const auto Cmp1 = MatchInfo.Cmp1;
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const auto Cmp2 = MatchInfo.Cmp2;
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const auto Diff = std::abs(Cmp2 - Cmp1);
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// If the difference between both comparison values is 0 or 1, there is no
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// need to clamp.
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if (Diff == 0 || Diff == 1)
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return false;
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const int64_t Min = std::numeric_limits<int16_t>::min();
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const int64_t Max = std::numeric_limits<int16_t>::max();
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// Check if the comparison values are between SHORT_MIN and SHORT_MAX.
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return ((Cmp2 >= Cmp1 && Cmp1 >= Min && Cmp2 <= Max) ||
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(Cmp1 >= Cmp2 && Cmp1 <= Max && Cmp2 >= Min));
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};
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// Try to match a combination of min / max MIR opcodes.
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if (mi_match(MI.getOperand(1).getReg(), MRI,
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m_GSMin(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) {
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if (mi_match(Base, MRI,
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m_GSMax(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) {
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return IsApplicableForCombine();
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}
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}
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if (mi_match(MI.getOperand(1).getReg(), MRI,
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m_GSMax(m_Reg(Base), m_ICst(MatchInfo.Cmp1)))) {
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if (mi_match(Base, MRI,
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m_GSMin(m_Reg(MatchInfo.Origin), m_ICst(MatchInfo.Cmp2)))) {
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return IsApplicableForCombine();
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}
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}
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return false;
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}
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// We want to find a combination of instructions that
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// gets generated when an i64 gets clamped to i16.
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// The corresponding pattern is:
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// G_MAX / G_MAX for i16 <= G_TRUNC i64.
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// This can be efficiently written as following:
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// v_cvt_pk_i16_i32 v0, v0, v1
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// v_med3_i32 v0, Clamp_Min, v0, Clamp_Max
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void AMDGPUPreLegalizerCombinerHelper::applyClampI64ToI16(
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MachineInstr &MI, const ClampI64ToI16MatchInfo &MatchInfo) {
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Register Src = MatchInfo.Origin;
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assert(MI.getParent()->getParent()->getRegInfo().getType(Src) ==
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LLT::scalar(64));
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const LLT S32 = LLT::scalar(32);
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B.setMBB(*MI.getParent());
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B.setInstrAndDebugLoc(MI);
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auto Unmerge = B.buildUnmerge(S32, Src);
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assert(MI.getOpcode() != AMDGPU::G_AMDGPU_CVT_PK_I16_I32);
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const LLT V2S16 = LLT::fixed_vector(2, 16);
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auto CvtPk =
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B.buildInstr(AMDGPU::G_AMDGPU_CVT_PK_I16_I32, {V2S16},
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{Unmerge.getReg(0), Unmerge.getReg(1)}, MI.getFlags());
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auto MinBoundary = std::min(MatchInfo.Cmp1, MatchInfo.Cmp2);
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auto MaxBoundary = std::max(MatchInfo.Cmp1, MatchInfo.Cmp2);
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auto MinBoundaryDst = B.buildConstant(S32, MinBoundary);
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auto MaxBoundaryDst = B.buildConstant(S32, MaxBoundary);
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auto Bitcast = B.buildBitcast({S32}, CvtPk);
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auto Med3 = B.buildInstr(
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AMDGPU::G_AMDGPU_SMED3, {S32},
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{MinBoundaryDst.getReg(0), Bitcast.getReg(0), MaxBoundaryDst.getReg(0)},
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MI.getFlags());
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B.buildTrunc(MI.getOperand(0).getReg(), Med3);
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MI.eraseFromParent();
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}
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class AMDGPUPreLegalizerCombinerHelperState {
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protected:
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CombinerHelper &Helper;
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AMDGPUPreLegalizerCombinerHelper &PreLegalizerHelper;
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public:
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AMDGPUPreLegalizerCombinerHelperState(
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CombinerHelper &Helper,
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AMDGPUPreLegalizerCombinerHelper &PreLegalizerHelper)
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: Helper(Helper), PreLegalizerHelper(PreLegalizerHelper) {}
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};
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#define AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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#include "AMDGPUGenPreLegalizeGICombiner.inc"
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#undef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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namespace {
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#define AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
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#include "AMDGPUGenPreLegalizeGICombiner.inc"
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#undef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
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class AMDGPUPreLegalizerCombinerInfo final : public CombinerInfo {
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GISelKnownBits *KB;
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MachineDominatorTree *MDT;
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public:
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AMDGPUGenPreLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
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AMDGPUPreLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
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GISelKnownBits *KB, MachineDominatorTree *MDT)
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: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
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/*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
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KB(KB), MDT(MDT) {
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if (!GeneratedRuleCfg.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
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MachineIRBuilder &B) const override;
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};
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bool AMDGPUPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
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MachineInstr &MI,
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MachineIRBuilder &B) const {
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CombinerHelper Helper(Observer, B, KB, MDT);
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AMDGPUPreLegalizerCombinerHelper PreLegalizerHelper(B, Helper);
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AMDGPUGenPreLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper,
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PreLegalizerHelper);
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if (Generated.tryCombineAll(Observer, MI, B, Helper))
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return true;
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switch (MI.getOpcode()) {
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case TargetOpcode::G_MEMCPY_INLINE:
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return Helper.tryEmitMemcpyInline(MI);
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case TargetOpcode::G_CONCAT_VECTORS:
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return Helper.tryCombineConcatVectors(MI);
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case TargetOpcode::G_SHUFFLE_VECTOR:
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return Helper.tryCombineShuffleVector(MI);
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}
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return false;
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}
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#define AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
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#include "AMDGPUGenPreLegalizeGICombiner.inc"
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#undef AMDGPUPRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
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// Pass boilerplate
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// ================
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class AMDGPUPreLegalizerCombiner : public MachineFunctionPass {
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public:
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static char ID;
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AMDGPUPreLegalizerCombiner(bool IsOptNone = false);
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StringRef getPassName() const override {
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return "AMDGPUPreLegalizerCombiner";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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private:
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bool IsOptNone;
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};
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} // end anonymous namespace
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void AMDGPUPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesCFG();
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getSelectionDAGFallbackAnalysisUsage(AU);
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AU.addRequired<GISelKnownBitsAnalysis>();
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AU.addPreserved<GISelKnownBitsAnalysis>();
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if (!IsOptNone) {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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AU.addRequired<GISelCSEAnalysisWrapperPass>();
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AU.addPreserved<GISelCSEAnalysisWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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AMDGPUPreLegalizerCombiner::AMDGPUPreLegalizerCombiner(bool IsOptNone)
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: MachineFunctionPass(ID), IsOptNone(IsOptNone) {
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initializeAMDGPUPreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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}
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bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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auto *TPC = &getAnalysis<TargetPassConfig>();
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const Function &F = MF.getFunction();
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bool EnableOpt =
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MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
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GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
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MachineDominatorTree *MDT =
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IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
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AMDGPUPreLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
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F.hasMinSize(), KB, MDT);
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// Enable CSE.
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GISelCSEAnalysisWrapper &Wrapper =
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getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
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auto *CSEInfo = &Wrapper.get(TPC->getCSEConfig());
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Combiner C(PCInfo, TPC);
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return C.combineMachineInstrs(MF, CSEInfo);
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}
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char AMDGPUPreLegalizerCombiner::ID = 0;
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INITIALIZE_PASS_BEGIN(AMDGPUPreLegalizerCombiner, DEBUG_TYPE,
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"Combine AMDGPU machine instrs before legalization",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
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INITIALIZE_PASS_END(AMDGPUPreLegalizerCombiner, DEBUG_TYPE,
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"Combine AMDGPU machine instrs before legalization", false,
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false)
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namespace llvm {
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FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone) {
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return new AMDGPUPreLegalizerCombiner(IsOptNone);
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}
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} // end namespace llvm
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