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https://github.com/RPCS3/llvm-mirror.git
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fd3020376e
Rename getBufferOffsetForMMO to updateBufferMMO and pass in the MMO to be updated, in preparation for the bug fix in D106284. Call updateBufferMMO consistently for all buffer intrinsics, even the ones that use setBufferOffsets to decompose a combined offset expression. Add a getIdxEn helper function. Differential Revision: https://reviews.llvm.org/D106354
499 lines
23 KiB
C++
499 lines
23 KiB
C++
//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// SI DAG Lowering interface definition
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
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#include "AMDGPUISelLowering.h"
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#include "AMDGPUArgumentUsageInfo.h"
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namespace llvm {
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class GCNSubtarget;
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class SIMachineFunctionInfo;
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class SIRegisterInfo;
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namespace AMDGPU {
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struct ImageDimIntrinsicInfo;
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}
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class SITargetLowering final : public AMDGPUTargetLowering {
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private:
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const GCNSubtarget *Subtarget;
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public:
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MVT getRegisterTypeForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const override;
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unsigned getNumRegistersForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const override;
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unsigned getVectorTypeBreakdownForCallingConv(
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LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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unsigned &NumIntermediates, MVT &RegisterVT) const override;
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private:
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SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
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SDValue Chain, uint64_t Offset) const;
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SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
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SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
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const SDLoc &SL, SDValue Chain,
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uint64_t Offset, Align Alignment,
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bool Signed,
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const ISD::InputArg *Arg = nullptr) const;
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SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
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const SDLoc &SL, SDValue Chain,
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const ISD::InputArg &Arg) const;
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SDValue getPreloadedValue(SelectionDAG &DAG,
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const SIMachineFunctionInfo &MFI,
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EVT VT,
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AMDGPUFunctionArgInfo::PreloadedValue) const;
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SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const override;
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SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
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MVT VT, unsigned Offset) const;
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SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
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SelectionDAG &DAG, bool WithChain) const;
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SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
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SDValue CachePolicy, SelectionDAG &DAG) const;
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SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
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unsigned NewOpcode) const;
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SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
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unsigned NewOpcode) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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// The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
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// (the offset that is included in bounds checking and swizzling, to be split
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// between the instruction's voffset and immoffset fields) and soffset (the
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// offset that is excluded from bounds checking and swizzling, to go in the
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// instruction's soffset field). This function takes the first kind of
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// offset and figures out how to split it between voffset and immoffset.
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std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
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SelectionDAG &DAG) const;
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SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
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SelectionDAG &DAG, ArrayRef<SDValue> Ops,
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bool IsIntrinsic = false) const;
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SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
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ArrayRef<SDValue> Ops) const;
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// Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
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// dwordx4 if on SI.
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SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
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ArrayRef<SDValue> Ops, EVT MemVT,
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MachineMemOperand *MMO, SelectionDAG &DAG) const;
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SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
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bool ImageStore = false) const;
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/// Converts \p Op, which must be of floating point type, to the
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/// floating point type \p VT, by either extending or truncating it.
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SDValue getFPExtOrFPRound(SelectionDAG &DAG,
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SDValue Op,
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const SDLoc &DL,
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EVT VT) const;
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SDValue convertArgType(
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SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
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bool Signed, const ISD::InputArg *Arg = nullptr) const;
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/// Custom lowering for ISD::FP_ROUND for MVT::f16.
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SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
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SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
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SelectionDAG &DAG) const;
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SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
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SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
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SDValue performUCharToFloatCombine(SDNode *N,
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DAGCombinerInfo &DCI) const;
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SDValue performSHLPtrCombine(SDNode *N,
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unsigned AS,
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EVT MemVT,
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DAGCombinerInfo &DCI) const;
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SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
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SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
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unsigned Opc, SDValue LHS,
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const ConstantSDNode *CRHS) const;
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SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
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const APFloat &C) const;
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SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
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SDValue Op0, SDValue Op1) const;
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SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
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SDValue Op0, SDValue Op1, bool Signed) const;
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SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
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unsigned getFusedOpcode(const SelectionDAG &DAG,
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const SDNode *N0, const SDNode *N1) const;
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SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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bool isLegalFlatAddressingMode(const AddrMode &AM) const;
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bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
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unsigned isCFIntrinsic(const SDNode *Intr) const;
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public:
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/// \returns True if fixup needs to be emitted for given global value \p GV,
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/// false otherwise.
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bool shouldEmitFixup(const GlobalValue *GV) const;
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/// \returns True if GOT relocation needs to be emitted for given global value
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/// \p GV, false otherwise.
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bool shouldEmitGOTReloc(const GlobalValue *GV) const;
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/// \returns True if PC-relative relocation needs to be emitted for given
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/// global value \p GV, false otherwise.
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bool shouldEmitPCReloc(const GlobalValue *GV) const;
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/// \returns true if this should use a literal constant for an LDS address,
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/// and not emit a relocation for an LDS global.
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bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
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/// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
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/// expanded into a set of cmp/select instructions.
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static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
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bool IsDivergentIdx);
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private:
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// Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
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// three offsets (voffset, soffset and instoffset) into the SDValue[3] array
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// pointed to by Offsets.
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void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
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SDValue *Offsets, Align Alignment = Align(4)) const;
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// Handle 8 bit and 16 bit buffer loads
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SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
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ArrayRef<SDValue> Ops, MemSDNode *M) const;
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// Handle 8 bit and 16 bit buffer stores
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SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
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SDLoc DL, SDValue Ops[],
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MemSDNode *M) const;
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public:
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SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
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const GCNSubtarget *getSubtarget() const;
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bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
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EVT SrcVT) const override;
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bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
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MachineFunction &MF,
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unsigned IntrinsicID) const override;
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bool getAddrModeArguments(IntrinsicInst * /*I*/,
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SmallVectorImpl<Value*> &/*Ops*/,
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Type *&/*AccessTy*/) const override;
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bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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bool canMergeStoresTo(unsigned AS, EVT MemVT,
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const SelectionDAG &DAG) const override;
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bool allowsMisalignedMemoryAccessesImpl(
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unsigned Size, unsigned AddrSpace, Align Alignment,
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MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
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bool *IsFast = nullptr) const;
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bool allowsMisalignedMemoryAccesses(
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LLT Ty, unsigned AddrSpace, Align Alignment,
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MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
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bool *IsFast = nullptr) const override {
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if (IsFast)
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*IsFast = false;
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return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace,
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Alignment, Flags, IsFast);
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}
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bool allowsMisalignedMemoryAccesses(
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EVT VT, unsigned AS, Align Alignment,
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MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
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bool *IsFast = nullptr) const override;
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EVT getOptimalMemOpType(const MemOp &Op,
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const AttributeList &FuncAttributes) const override;
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bool isMemOpUniform(const SDNode *N) const;
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bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
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static bool isNonGlobalAddrSpace(unsigned AS);
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bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
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TargetLoweringBase::LegalizeTypeAction
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getPreferredVectorAction(MVT VT) const override;
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override;
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bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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bool supportSplitCSR(MachineFunction *MF) const override;
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void initializeSplitCSR(MachineBasicBlock *Entry) const override;
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void insertCopiesSplitCSR(
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MachineBasicBlock *Entry,
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const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv,
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MachineFunction &MF, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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void passSpecialInputs(
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CallLoweringInfo &CLI,
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CCState &CCInfo,
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const SIMachineFunctionInfo &Info,
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SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
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SmallVectorImpl<SDValue> &MemOpChains,
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SDValue Chain) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
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SDValue ThisVal) const;
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bool mayBeEmittedAsTailCall(const CallInst *) const override;
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bool isEligibleForTailCallOptimization(
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SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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Register getRegisterByName(const char* RegName, LLT VT,
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const MachineFunction &MF) const override;
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MachineBasicBlock *splitKillBlock(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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void bundleInstWithWaitcnt(MachineInstr &MI) const;
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MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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bool hasBitPreservingFPLogic(EVT VT) const override;
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bool enableAggressiveFMAFusion(EVT VT) const override;
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
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LLT getPreferredShiftAmountTy(LLT Ty) const override;
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bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
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EVT VT) const override;
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bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
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SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
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SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
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SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
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void AddIMGInit(MachineInstr &MI) const;
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void AdjustInstrPostInstrSelection(MachineInstr &MI,
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SDNode *Node) const override;
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SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
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MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
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SDValue Ptr) const;
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MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
|
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uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
|
|
std::pair<unsigned, const TargetRegisterClass *>
|
|
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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|
StringRef Constraint, MVT VT) const override;
|
|
ConstraintType getConstraintType(StringRef Constraint) const override;
|
|
void LowerAsmOperandForConstraint(SDValue Op,
|
|
std::string &Constraint,
|
|
std::vector<SDValue> &Ops,
|
|
SelectionDAG &DAG) const override;
|
|
bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
|
|
bool checkAsmConstraintVal(SDValue Op,
|
|
const std::string &Constraint,
|
|
uint64_t Val) const;
|
|
bool checkAsmConstraintValA(SDValue Op,
|
|
uint64_t Val,
|
|
unsigned MaxSize = 64) const;
|
|
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
|
|
SDValue V) const;
|
|
|
|
void finalizeLowering(MachineFunction &MF) const override;
|
|
|
|
void computeKnownBitsForFrameIndex(int FrameIdx,
|
|
KnownBits &Known,
|
|
const MachineFunction &MF) const override;
|
|
void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R,
|
|
KnownBits &Known,
|
|
const APInt &DemandedElts,
|
|
const MachineRegisterInfo &MRI,
|
|
unsigned Depth = 0) const override;
|
|
|
|
Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R,
|
|
const MachineRegisterInfo &MRI,
|
|
unsigned Depth = 0) const override;
|
|
bool isSDNodeSourceOfDivergence(const SDNode *N,
|
|
FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
|
|
|
|
bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
|
|
unsigned MaxDepth = 5) const;
|
|
bool isCanonicalized(Register Reg, MachineFunction &MF,
|
|
unsigned MaxDepth = 5) const;
|
|
bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
|
|
bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const;
|
|
|
|
bool isKnownNeverNaNForTargetNode(SDValue Op,
|
|
const SelectionDAG &DAG,
|
|
bool SNaN = false,
|
|
unsigned Depth = 0) const override;
|
|
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
|
|
|
|
virtual const TargetRegisterClass *
|
|
getRegClassFor(MVT VT, bool isDivergent) const override;
|
|
virtual bool requiresUniformRegister(MachineFunction &MF,
|
|
const Value *V) const override;
|
|
Align getPrefLoopAlignment(MachineLoop *ML) const override;
|
|
|
|
void allocateHSAUserSGPRs(CCState &CCInfo,
|
|
MachineFunction &MF,
|
|
const SIRegisterInfo &TRI,
|
|
SIMachineFunctionInfo &Info) const;
|
|
|
|
void allocateSystemSGPRs(CCState &CCInfo,
|
|
MachineFunction &MF,
|
|
SIMachineFunctionInfo &Info,
|
|
CallingConv::ID CallConv,
|
|
bool IsShader) const;
|
|
|
|
void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
|
|
MachineFunction &MF,
|
|
const SIRegisterInfo &TRI,
|
|
SIMachineFunctionInfo &Info) const;
|
|
void allocateSpecialInputSGPRs(
|
|
CCState &CCInfo,
|
|
MachineFunction &MF,
|
|
const SIRegisterInfo &TRI,
|
|
SIMachineFunctionInfo &Info) const;
|
|
|
|
void allocateSpecialInputVGPRs(CCState &CCInfo,
|
|
MachineFunction &MF,
|
|
const SIRegisterInfo &TRI,
|
|
SIMachineFunctionInfo &Info) const;
|
|
void allocateSpecialInputVGPRsFixed(CCState &CCInfo,
|
|
MachineFunction &MF,
|
|
const SIRegisterInfo &TRI,
|
|
SIMachineFunctionInfo &Info) const;
|
|
|
|
std::pair<InstructionCost, MVT> getTypeLegalizationCost(const DataLayout &DL,
|
|
Type *Ty) const;
|
|
};
|
|
|
|
} // End namespace llvm
|
|
|
|
#endif
|