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e872e10570
Serialize ScavengeFI from SIMachineFunctionInfo into yaml. ScavengeFI is not used outside of the PrologEpilogInserter, so this shouldn't change anything. Differential Revision: https://reviews.llvm.org/D101367
954 lines
28 KiB
C++
954 lines
28 KiB
C++
//==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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#include "AMDGPUArgumentUsageInfo.h"
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#include "AMDGPUMachineFunction.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIInstrInfo.h"
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#include "llvm/ADT/MapVector.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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class MachineFrameInfo;
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class MachineFunction;
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class TargetRegisterClass;
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class SIMachineFunctionInfo;
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class SIRegisterInfo;
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class AMDGPUPseudoSourceValue : public PseudoSourceValue {
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public:
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enum AMDGPUPSVKind : unsigned {
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PSVBuffer = PseudoSourceValue::TargetCustom,
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PSVImage,
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GWSResource
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};
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protected:
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AMDGPUPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII)
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: PseudoSourceValue(Kind, TII) {}
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public:
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bool isConstant(const MachineFrameInfo *) const override {
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// This should probably be true for most images, but we will start by being
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// conservative.
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return false;
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}
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bool isAliased(const MachineFrameInfo *) const override {
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return true;
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}
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bool mayAlias(const MachineFrameInfo *) const override {
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return true;
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}
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};
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class AMDGPUBufferPseudoSourceValue final : public AMDGPUPseudoSourceValue {
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public:
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explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII)
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: AMDGPUPseudoSourceValue(PSVBuffer, TII) {}
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static bool classof(const PseudoSourceValue *V) {
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return V->kind() == PSVBuffer;
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}
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void printCustom(raw_ostream &OS) const override { OS << "BufferResource"; }
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};
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class AMDGPUImagePseudoSourceValue final : public AMDGPUPseudoSourceValue {
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public:
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// TODO: Is the img rsrc useful?
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explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII)
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: AMDGPUPseudoSourceValue(PSVImage, TII) {}
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static bool classof(const PseudoSourceValue *V) {
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return V->kind() == PSVImage;
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}
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void printCustom(raw_ostream &OS) const override { OS << "ImageResource"; }
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};
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class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
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public:
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explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII)
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: AMDGPUPseudoSourceValue(GWSResource, TII) {}
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static bool classof(const PseudoSourceValue *V) {
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return V->kind() == GWSResource;
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}
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// These are inaccessible memory from IR.
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bool isAliased(const MachineFrameInfo *) const override {
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return false;
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}
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// These are inaccessible memory from IR.
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bool mayAlias(const MachineFrameInfo *) const override {
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return false;
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}
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void printCustom(raw_ostream &OS) const override {
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OS << "GWSResource";
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}
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};
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namespace yaml {
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struct SIArgument {
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bool IsRegister;
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union {
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StringValue RegisterName;
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unsigned StackOffset;
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};
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Optional<unsigned> Mask;
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// Default constructor, which creates a stack argument.
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SIArgument() : IsRegister(false), StackOffset(0) {}
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SIArgument(const SIArgument &Other) {
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IsRegister = Other.IsRegister;
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if (IsRegister) {
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::new ((void *)std::addressof(RegisterName))
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StringValue(Other.RegisterName);
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} else
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StackOffset = Other.StackOffset;
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Mask = Other.Mask;
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}
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SIArgument &operator=(const SIArgument &Other) {
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IsRegister = Other.IsRegister;
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if (IsRegister) {
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::new ((void *)std::addressof(RegisterName))
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StringValue(Other.RegisterName);
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} else
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StackOffset = Other.StackOffset;
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Mask = Other.Mask;
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return *this;
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}
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~SIArgument() {
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if (IsRegister)
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RegisterName.~StringValue();
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}
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// Helper to create a register or stack argument.
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static inline SIArgument createArgument(bool IsReg) {
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if (IsReg)
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return SIArgument(IsReg);
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return SIArgument();
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}
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private:
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// Construct a register argument.
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SIArgument(bool) : IsRegister(true), RegisterName() {}
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};
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template <> struct MappingTraits<SIArgument> {
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static void mapping(IO &YamlIO, SIArgument &A) {
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if (YamlIO.outputting()) {
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if (A.IsRegister)
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YamlIO.mapRequired("reg", A.RegisterName);
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else
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YamlIO.mapRequired("offset", A.StackOffset);
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} else {
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auto Keys = YamlIO.keys();
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if (is_contained(Keys, "reg")) {
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A = SIArgument::createArgument(true);
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YamlIO.mapRequired("reg", A.RegisterName);
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} else if (is_contained(Keys, "offset"))
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YamlIO.mapRequired("offset", A.StackOffset);
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else
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YamlIO.setError("missing required key 'reg' or 'offset'");
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}
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YamlIO.mapOptional("mask", A.Mask);
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}
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static const bool flow = true;
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};
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struct SIArgumentInfo {
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Optional<SIArgument> PrivateSegmentBuffer;
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Optional<SIArgument> DispatchPtr;
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Optional<SIArgument> QueuePtr;
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Optional<SIArgument> KernargSegmentPtr;
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Optional<SIArgument> DispatchID;
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Optional<SIArgument> FlatScratchInit;
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Optional<SIArgument> PrivateSegmentSize;
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Optional<SIArgument> WorkGroupIDX;
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Optional<SIArgument> WorkGroupIDY;
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Optional<SIArgument> WorkGroupIDZ;
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Optional<SIArgument> WorkGroupInfo;
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Optional<SIArgument> PrivateSegmentWaveByteOffset;
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Optional<SIArgument> ImplicitArgPtr;
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Optional<SIArgument> ImplicitBufferPtr;
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Optional<SIArgument> WorkItemIDX;
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Optional<SIArgument> WorkItemIDY;
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Optional<SIArgument> WorkItemIDZ;
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};
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template <> struct MappingTraits<SIArgumentInfo> {
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static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
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YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer);
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YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr);
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YamlIO.mapOptional("queuePtr", AI.QueuePtr);
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YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr);
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YamlIO.mapOptional("dispatchID", AI.DispatchID);
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YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit);
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YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize);
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YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX);
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YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY);
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YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ);
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YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo);
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YamlIO.mapOptional("privateSegmentWaveByteOffset",
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AI.PrivateSegmentWaveByteOffset);
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YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr);
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YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr);
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YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX);
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YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
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YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
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}
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};
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// Default to default mode for default calling convention.
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struct SIMode {
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bool IEEE = true;
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bool DX10Clamp = true;
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bool FP32InputDenormals = true;
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bool FP32OutputDenormals = true;
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bool FP64FP16InputDenormals = true;
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bool FP64FP16OutputDenormals = true;
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SIMode() = default;
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SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
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IEEE = Mode.IEEE;
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DX10Clamp = Mode.DX10Clamp;
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FP32InputDenormals = Mode.FP32InputDenormals;
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FP32OutputDenormals = Mode.FP32OutputDenormals;
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FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
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FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
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}
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bool operator ==(const SIMode Other) const {
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return IEEE == Other.IEEE &&
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DX10Clamp == Other.DX10Clamp &&
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FP32InputDenormals == Other.FP32InputDenormals &&
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FP32OutputDenormals == Other.FP32OutputDenormals &&
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FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
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FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
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}
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};
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template <> struct MappingTraits<SIMode> {
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static void mapping(IO &YamlIO, SIMode &Mode) {
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YamlIO.mapOptional("ieee", Mode.IEEE, true);
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YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
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YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
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YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
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YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
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YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
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}
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};
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struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
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uint64_t ExplicitKernArgSize = 0;
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unsigned MaxKernArgAlign = 0;
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unsigned LDSSize = 0;
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Align DynLDSAlign;
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bool IsEntryFunction = false;
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bool NoSignedZerosFPMath = false;
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bool MemoryBound = false;
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bool WaveLimiter = false;
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bool HasSpilledSGPRs = false;
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bool HasSpilledVGPRs = false;
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uint32_t HighBitsOf32BitAddress = 0;
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// TODO: 10 may be a better default since it's the maximum.
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unsigned Occupancy = 0;
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StringValue ScratchRSrcReg = "$private_rsrc_reg";
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StringValue FrameOffsetReg = "$fp_reg";
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StringValue StackPtrOffsetReg = "$sp_reg";
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Optional<SIArgumentInfo> ArgInfo;
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SIMode Mode;
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Optional<FrameIndex> ScavengeFI;
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SIMachineFunctionInfo() = default;
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SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
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const TargetRegisterInfo &TRI,
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const llvm::MachineFunction &MF);
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void mappingImpl(yaml::IO &YamlIO) override;
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~SIMachineFunctionInfo() = default;
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};
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template <> struct MappingTraits<SIMachineFunctionInfo> {
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static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
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YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
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UINT64_C(0));
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YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
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YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
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YamlIO.mapOptional("dynLDSAlign", MFI.DynLDSAlign, Align());
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YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
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YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
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YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
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YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
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YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false);
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YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false);
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YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
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StringValue("$private_rsrc_reg"));
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YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
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StringValue("$fp_reg"));
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YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
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StringValue("$sp_reg"));
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YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
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YamlIO.mapOptional("mode", MFI.Mode, SIMode());
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YamlIO.mapOptional("highBitsOf32BitAddress",
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MFI.HighBitsOf32BitAddress, 0u);
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YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
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YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
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}
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};
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} // end namespace yaml
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/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
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/// tells the hardware which interpolation parameters to load.
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class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
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friend class GCNTargetMachine;
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Register TIDReg = AMDGPU::NoRegister;
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// Registers that may be reserved for spilling purposes. These may be the same
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// as the input registers.
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Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
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// This is the the unswizzled offset from the current dispatch's scratch wave
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// base to the beginning of the current function's frame.
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Register FrameOffsetReg = AMDGPU::FP_REG;
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// This is an ABI register used in the non-entry calling convention to
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// communicate the unswizzled offset from the current dispatch's scratch wave
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// base to the beginning of the new function's frame.
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Register StackPtrOffsetReg = AMDGPU::SP_REG;
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AMDGPUFunctionArgInfo ArgInfo;
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// Graphics info.
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unsigned PSInputAddr = 0;
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unsigned PSInputEnable = 0;
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/// Number of bytes of arguments this function has on the stack. If the callee
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/// is expected to restore the argument stack this should be a multiple of 16,
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/// all usable during a tail call.
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///
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/// The alternative would forbid tail call optimisation in some cases: if we
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/// want to transfer control from a function with 8-bytes of stack-argument
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/// space to a function with 16-bytes then misalignment of this value would
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/// make a stack adjustment necessary, which could not be undone by the
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/// callee.
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unsigned BytesInStackArgArea = 0;
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bool ReturnsVoid = true;
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// A pair of default/requested minimum/maximum flat work group sizes.
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// Minimum - first, maximum - second.
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std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
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// A pair of default/requested minimum/maximum number of waves per execution
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// unit. Minimum - first, maximum - second.
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std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
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std::unique_ptr<const AMDGPUBufferPseudoSourceValue> BufferPSV;
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std::unique_ptr<const AMDGPUImagePseudoSourceValue> ImagePSV;
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std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
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private:
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unsigned LDSWaveSpillSize = 0;
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unsigned NumUserSGPRs = 0;
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unsigned NumSystemSGPRs = 0;
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bool HasSpilledSGPRs = false;
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bool HasSpilledVGPRs = false;
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bool HasNonSpillStackObjects = false;
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bool IsStackRealigned = false;
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unsigned NumSpilledSGPRs = 0;
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unsigned NumSpilledVGPRs = 0;
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// Feature bits required for inputs passed in user SGPRs.
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bool PrivateSegmentBuffer : 1;
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bool DispatchPtr : 1;
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bool QueuePtr : 1;
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bool KernargSegmentPtr : 1;
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bool DispatchID : 1;
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bool FlatScratchInit : 1;
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// Feature bits required for inputs passed in system SGPRs.
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bool WorkGroupIDX : 1; // Always initialized.
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bool WorkGroupIDY : 1;
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bool WorkGroupIDZ : 1;
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bool WorkGroupInfo : 1;
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bool PrivateSegmentWaveByteOffset : 1;
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bool WorkItemIDX : 1; // Always initialized.
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bool WorkItemIDY : 1;
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bool WorkItemIDZ : 1;
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// Private memory buffer
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// Compute directly in sgpr[0:1]
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// Other shaders indirect 64-bits at sgpr[0:1]
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bool ImplicitBufferPtr : 1;
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// Pointer to where the ABI inserts special kernel arguments separate from the
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// user arguments. This is an offset from the KernargSegmentPtr.
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bool ImplicitArgPtr : 1;
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// The hard-wired high half of the address of the global information table
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// for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
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// current hardware only allows a 16 bit value.
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unsigned GITPtrHigh;
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unsigned HighBitsOf32BitAddress;
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unsigned GDSSize;
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// Current recorded maximum possible occupancy.
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unsigned Occupancy;
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MCPhysReg getNextUserSGPR() const;
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MCPhysReg getNextSystemSGPR() const;
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public:
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struct SpilledReg {
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Register VGPR;
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int Lane = -1;
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SpilledReg() = default;
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SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
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bool hasLane() { return Lane != -1;}
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bool hasReg() { return VGPR != 0;}
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};
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struct SGPRSpillVGPR {
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// VGPR used for SGPR spills
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Register VGPR;
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// If the VGPR is is used for SGPR spills in a non-entrypoint function, the
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// stack slot used to save/restore it in the prolog/epilog.
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Optional<int> FI;
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SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
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};
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struct VGPRSpillToAGPR {
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SmallVector<MCPhysReg, 32> Lanes;
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bool FullyAllocated = false;
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};
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// Map WWM VGPR to a stack slot that is used to save/restore it in the
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// prolog/epilog.
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MapVector<Register, Optional<int>> WWMReservedRegs;
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private:
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// Track VGPR + wave index for each subregister of the SGPR spilled to
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// frameindex key.
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DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
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unsigned NumVGPRSpillLanes = 0;
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SmallVector<SGPRSpillVGPR, 2> SpillVGPRs;
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DenseMap<int, VGPRSpillToAGPR> VGPRToAGPRSpills;
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// AGPRs used for VGPR spills.
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SmallVector<MCPhysReg, 32> SpillAGPR;
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// VGPRs used for AGPR spills.
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SmallVector<MCPhysReg, 32> SpillVGPR;
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// Emergency stack slot. Sometimes, we create this before finalizing the stack
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// frame, so save it here and add it to the RegScavenger later.
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Optional<int> ScavengeFI;
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|
|
|
public: // FIXME
|
|
/// If this is set, an SGPR used for save/restore of the register used for the
|
|
/// frame pointer.
|
|
Register SGPRForFPSaveRestoreCopy;
|
|
Optional<int> FramePointerSaveIndex;
|
|
|
|
/// If this is set, an SGPR used for save/restore of the register used for the
|
|
/// base pointer.
|
|
Register SGPRForBPSaveRestoreCopy;
|
|
Optional<int> BasePointerSaveIndex;
|
|
|
|
Register VGPRReservedForSGPRSpill;
|
|
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg);
|
|
|
|
public:
|
|
SIMachineFunctionInfo(const MachineFunction &MF);
|
|
|
|
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI,
|
|
const MachineFunction &MF,
|
|
PerFunctionMIParsingState &PFS,
|
|
SMDiagnostic &Error, SMRange &SourceRange);
|
|
|
|
void reserveWWMRegister(Register Reg, Optional<int> FI) {
|
|
WWMReservedRegs.insert(std::make_pair(Reg, FI));
|
|
}
|
|
|
|
ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
|
|
auto I = SGPRToVGPRSpills.find(FrameIndex);
|
|
return (I == SGPRToVGPRSpills.end()) ?
|
|
ArrayRef<SpilledReg>() : makeArrayRef(I->second);
|
|
}
|
|
|
|
ArrayRef<SGPRSpillVGPR> getSGPRSpillVGPRs() const { return SpillVGPRs; }
|
|
|
|
void setSGPRSpillVGPRs(Register NewVGPR, Optional<int> newFI, int Index) {
|
|
SpillVGPRs[Index].VGPR = NewVGPR;
|
|
SpillVGPRs[Index].FI = newFI;
|
|
VGPRReservedForSGPRSpill = NewVGPR;
|
|
}
|
|
|
|
bool removeVGPRForSGPRSpill(Register ReservedVGPR, MachineFunction &MF);
|
|
|
|
ArrayRef<MCPhysReg> getAGPRSpillVGPRs() const {
|
|
return SpillAGPR;
|
|
}
|
|
|
|
ArrayRef<MCPhysReg> getVGPRSpillAGPRs() const {
|
|
return SpillVGPR;
|
|
}
|
|
|
|
MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
|
|
auto I = VGPRToAGPRSpills.find(FrameIndex);
|
|
return (I == VGPRToAGPRSpills.end()) ? (MCPhysReg)AMDGPU::NoRegister
|
|
: I->second.Lanes[Lane];
|
|
}
|
|
|
|
bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
|
|
unsigned NumLane) const;
|
|
bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
|
|
bool reserveVGPRforSGPRSpills(MachineFunction &MF);
|
|
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
|
|
void removeDeadFrameIndices(MachineFrameInfo &MFI);
|
|
|
|
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI);
|
|
Optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
|
|
|
|
bool hasCalculatedTID() const { return TIDReg != 0; };
|
|
Register getTIDReg() const { return TIDReg; };
|
|
void setTIDReg(Register Reg) { TIDReg = Reg; }
|
|
|
|
unsigned getBytesInStackArgArea() const {
|
|
return BytesInStackArgArea;
|
|
}
|
|
|
|
void setBytesInStackArgArea(unsigned Bytes) {
|
|
BytesInStackArgArea = Bytes;
|
|
}
|
|
|
|
// Add user SGPRs.
|
|
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
|
|
Register addDispatchPtr(const SIRegisterInfo &TRI);
|
|
Register addQueuePtr(const SIRegisterInfo &TRI);
|
|
Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
|
|
Register addDispatchID(const SIRegisterInfo &TRI);
|
|
Register addFlatScratchInit(const SIRegisterInfo &TRI);
|
|
Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
|
|
|
|
// Add system SGPRs.
|
|
Register addWorkGroupIDX() {
|
|
ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
|
|
NumSystemSGPRs += 1;
|
|
return ArgInfo.WorkGroupIDX.getRegister();
|
|
}
|
|
|
|
Register addWorkGroupIDY() {
|
|
ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
|
|
NumSystemSGPRs += 1;
|
|
return ArgInfo.WorkGroupIDY.getRegister();
|
|
}
|
|
|
|
Register addWorkGroupIDZ() {
|
|
ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
|
|
NumSystemSGPRs += 1;
|
|
return ArgInfo.WorkGroupIDZ.getRegister();
|
|
}
|
|
|
|
Register addWorkGroupInfo() {
|
|
ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
|
|
NumSystemSGPRs += 1;
|
|
return ArgInfo.WorkGroupInfo.getRegister();
|
|
}
|
|
|
|
// Add special VGPR inputs
|
|
void setWorkItemIDX(ArgDescriptor Arg) {
|
|
ArgInfo.WorkItemIDX = Arg;
|
|
}
|
|
|
|
void setWorkItemIDY(ArgDescriptor Arg) {
|
|
ArgInfo.WorkItemIDY = Arg;
|
|
}
|
|
|
|
void setWorkItemIDZ(ArgDescriptor Arg) {
|
|
ArgInfo.WorkItemIDZ = Arg;
|
|
}
|
|
|
|
Register addPrivateSegmentWaveByteOffset() {
|
|
ArgInfo.PrivateSegmentWaveByteOffset
|
|
= ArgDescriptor::createRegister(getNextSystemSGPR());
|
|
NumSystemSGPRs += 1;
|
|
return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
|
|
}
|
|
|
|
void setPrivateSegmentWaveByteOffset(Register Reg) {
|
|
ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
|
|
}
|
|
|
|
bool hasPrivateSegmentBuffer() const {
|
|
return PrivateSegmentBuffer;
|
|
}
|
|
|
|
bool hasDispatchPtr() const {
|
|
return DispatchPtr;
|
|
}
|
|
|
|
bool hasQueuePtr() const {
|
|
return QueuePtr;
|
|
}
|
|
|
|
bool hasKernargSegmentPtr() const {
|
|
return KernargSegmentPtr;
|
|
}
|
|
|
|
bool hasDispatchID() const {
|
|
return DispatchID;
|
|
}
|
|
|
|
bool hasFlatScratchInit() const {
|
|
return FlatScratchInit;
|
|
}
|
|
|
|
bool hasWorkGroupIDX() const {
|
|
return WorkGroupIDX;
|
|
}
|
|
|
|
bool hasWorkGroupIDY() const {
|
|
return WorkGroupIDY;
|
|
}
|
|
|
|
bool hasWorkGroupIDZ() const {
|
|
return WorkGroupIDZ;
|
|
}
|
|
|
|
bool hasWorkGroupInfo() const {
|
|
return WorkGroupInfo;
|
|
}
|
|
|
|
bool hasPrivateSegmentWaveByteOffset() const {
|
|
return PrivateSegmentWaveByteOffset;
|
|
}
|
|
|
|
bool hasWorkItemIDX() const {
|
|
return WorkItemIDX;
|
|
}
|
|
|
|
bool hasWorkItemIDY() const {
|
|
return WorkItemIDY;
|
|
}
|
|
|
|
bool hasWorkItemIDZ() const {
|
|
return WorkItemIDZ;
|
|
}
|
|
|
|
bool hasImplicitArgPtr() const {
|
|
return ImplicitArgPtr;
|
|
}
|
|
|
|
bool hasImplicitBufferPtr() const {
|
|
return ImplicitBufferPtr;
|
|
}
|
|
|
|
AMDGPUFunctionArgInfo &getArgInfo() {
|
|
return ArgInfo;
|
|
}
|
|
|
|
const AMDGPUFunctionArgInfo &getArgInfo() const {
|
|
return ArgInfo;
|
|
}
|
|
|
|
std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
|
|
getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
|
|
return ArgInfo.getPreloadedValue(Value);
|
|
}
|
|
|
|
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
|
|
auto Arg = std::get<0>(ArgInfo.getPreloadedValue(Value));
|
|
return Arg ? Arg->getRegister() : MCRegister();
|
|
}
|
|
|
|
unsigned getGITPtrHigh() const {
|
|
return GITPtrHigh;
|
|
}
|
|
|
|
Register getGITPtrLoReg(const MachineFunction &MF) const;
|
|
|
|
uint32_t get32BitAddressHighBits() const {
|
|
return HighBitsOf32BitAddress;
|
|
}
|
|
|
|
unsigned getGDSSize() const {
|
|
return GDSSize;
|
|
}
|
|
|
|
unsigned getNumUserSGPRs() const {
|
|
return NumUserSGPRs;
|
|
}
|
|
|
|
unsigned getNumPreloadedSGPRs() const {
|
|
return NumUserSGPRs + NumSystemSGPRs;
|
|
}
|
|
|
|
Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
|
|
return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
|
|
}
|
|
|
|
/// Returns the physical register reserved for use as the resource
|
|
/// descriptor for scratch accesses.
|
|
Register getScratchRSrcReg() const {
|
|
return ScratchRSrcReg;
|
|
}
|
|
|
|
void setScratchRSrcReg(Register Reg) {
|
|
assert(Reg != 0 && "Should never be unset");
|
|
ScratchRSrcReg = Reg;
|
|
}
|
|
|
|
Register getFrameOffsetReg() const {
|
|
return FrameOffsetReg;
|
|
}
|
|
|
|
void setFrameOffsetReg(Register Reg) {
|
|
assert(Reg != 0 && "Should never be unset");
|
|
FrameOffsetReg = Reg;
|
|
}
|
|
|
|
void setStackPtrOffsetReg(Register Reg) {
|
|
assert(Reg != 0 && "Should never be unset");
|
|
StackPtrOffsetReg = Reg;
|
|
}
|
|
|
|
// Note the unset value for this is AMDGPU::SP_REG rather than
|
|
// NoRegister. This is mostly a workaround for MIR tests where state that
|
|
// can't be directly computed from the function is not preserved in serialized
|
|
// MIR.
|
|
Register getStackPtrOffsetReg() const {
|
|
return StackPtrOffsetReg;
|
|
}
|
|
|
|
Register getQueuePtrUserSGPR() const {
|
|
return ArgInfo.QueuePtr.getRegister();
|
|
}
|
|
|
|
Register getImplicitBufferPtrUserSGPR() const {
|
|
return ArgInfo.ImplicitBufferPtr.getRegister();
|
|
}
|
|
|
|
bool hasSpilledSGPRs() const {
|
|
return HasSpilledSGPRs;
|
|
}
|
|
|
|
void setHasSpilledSGPRs(bool Spill = true) {
|
|
HasSpilledSGPRs = Spill;
|
|
}
|
|
|
|
bool hasSpilledVGPRs() const {
|
|
return HasSpilledVGPRs;
|
|
}
|
|
|
|
void setHasSpilledVGPRs(bool Spill = true) {
|
|
HasSpilledVGPRs = Spill;
|
|
}
|
|
|
|
bool hasNonSpillStackObjects() const {
|
|
return HasNonSpillStackObjects;
|
|
}
|
|
|
|
void setHasNonSpillStackObjects(bool StackObject = true) {
|
|
HasNonSpillStackObjects = StackObject;
|
|
}
|
|
|
|
bool isStackRealigned() const {
|
|
return IsStackRealigned;
|
|
}
|
|
|
|
void setIsStackRealigned(bool Realigned = true) {
|
|
IsStackRealigned = Realigned;
|
|
}
|
|
|
|
unsigned getNumSpilledSGPRs() const {
|
|
return NumSpilledSGPRs;
|
|
}
|
|
|
|
unsigned getNumSpilledVGPRs() const {
|
|
return NumSpilledVGPRs;
|
|
}
|
|
|
|
void addToSpilledSGPRs(unsigned num) {
|
|
NumSpilledSGPRs += num;
|
|
}
|
|
|
|
void addToSpilledVGPRs(unsigned num) {
|
|
NumSpilledVGPRs += num;
|
|
}
|
|
|
|
unsigned getPSInputAddr() const {
|
|
return PSInputAddr;
|
|
}
|
|
|
|
unsigned getPSInputEnable() const {
|
|
return PSInputEnable;
|
|
}
|
|
|
|
bool isPSInputAllocated(unsigned Index) const {
|
|
return PSInputAddr & (1 << Index);
|
|
}
|
|
|
|
void markPSInputAllocated(unsigned Index) {
|
|
PSInputAddr |= 1 << Index;
|
|
}
|
|
|
|
void markPSInputEnabled(unsigned Index) {
|
|
PSInputEnable |= 1 << Index;
|
|
}
|
|
|
|
bool returnsVoid() const {
|
|
return ReturnsVoid;
|
|
}
|
|
|
|
void setIfReturnsVoid(bool Value) {
|
|
ReturnsVoid = Value;
|
|
}
|
|
|
|
/// \returns A pair of default/requested minimum/maximum flat work group sizes
|
|
/// for this function.
|
|
std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
|
|
return FlatWorkGroupSizes;
|
|
}
|
|
|
|
/// \returns Default/requested minimum flat work group size for this function.
|
|
unsigned getMinFlatWorkGroupSize() const {
|
|
return FlatWorkGroupSizes.first;
|
|
}
|
|
|
|
/// \returns Default/requested maximum flat work group size for this function.
|
|
unsigned getMaxFlatWorkGroupSize() const {
|
|
return FlatWorkGroupSizes.second;
|
|
}
|
|
|
|
/// \returns A pair of default/requested minimum/maximum number of waves per
|
|
/// execution unit.
|
|
std::pair<unsigned, unsigned> getWavesPerEU() const {
|
|
return WavesPerEU;
|
|
}
|
|
|
|
/// \returns Default/requested minimum number of waves per execution unit.
|
|
unsigned getMinWavesPerEU() const {
|
|
return WavesPerEU.first;
|
|
}
|
|
|
|
/// \returns Default/requested maximum number of waves per execution unit.
|
|
unsigned getMaxWavesPerEU() const {
|
|
return WavesPerEU.second;
|
|
}
|
|
|
|
/// \returns SGPR used for \p Dim's work group ID.
|
|
Register getWorkGroupIDSGPR(unsigned Dim) const {
|
|
switch (Dim) {
|
|
case 0:
|
|
assert(hasWorkGroupIDX());
|
|
return ArgInfo.WorkGroupIDX.getRegister();
|
|
case 1:
|
|
assert(hasWorkGroupIDY());
|
|
return ArgInfo.WorkGroupIDY.getRegister();
|
|
case 2:
|
|
assert(hasWorkGroupIDZ());
|
|
return ArgInfo.WorkGroupIDZ.getRegister();
|
|
}
|
|
llvm_unreachable("unexpected dimension");
|
|
}
|
|
|
|
unsigned getLDSWaveSpillSize() const {
|
|
return LDSWaveSpillSize;
|
|
}
|
|
|
|
const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII) {
|
|
if (!BufferPSV)
|
|
BufferPSV = std::make_unique<AMDGPUBufferPseudoSourceValue>(TII);
|
|
|
|
return BufferPSV.get();
|
|
}
|
|
|
|
const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII) {
|
|
if (!ImagePSV)
|
|
ImagePSV = std::make_unique<AMDGPUImagePseudoSourceValue>(TII);
|
|
|
|
return ImagePSV.get();
|
|
}
|
|
|
|
const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
|
|
if (!GWSResourcePSV) {
|
|
GWSResourcePSV =
|
|
std::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
|
|
}
|
|
|
|
return GWSResourcePSV.get();
|
|
}
|
|
|
|
unsigned getOccupancy() const {
|
|
return Occupancy;
|
|
}
|
|
|
|
unsigned getMinAllowedOccupancy() const {
|
|
if (!isMemoryBound() && !needsWaveLimiter())
|
|
return Occupancy;
|
|
return (Occupancy < 4) ? Occupancy : 4;
|
|
}
|
|
|
|
void limitOccupancy(const MachineFunction &MF);
|
|
|
|
void limitOccupancy(unsigned Limit) {
|
|
if (Occupancy > Limit)
|
|
Occupancy = Limit;
|
|
}
|
|
|
|
void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
|
|
if (Occupancy < Limit)
|
|
Occupancy = Limit;
|
|
limitOccupancy(MF);
|
|
}
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
|