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51b479815c
This is required in order to determine during disassembly whether a Reg bead without associated DA bead is referring to a data register. Differential Revision: https://reviews.llvm.org/D98534
372 lines
16 KiB
TableGen
372 lines
16 KiB
TableGen
//=== M68kInstrFormats.td - M68k Instruction Formats ---*- tablegen -*-===//
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// The LLVM Compiler Infrastructure
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains M68k instruction formats.
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///
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/// Since M68k has quite a lot memory addressing modes there are more
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/// instruction prefixes than just i, r and m:
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/// TSF Since Form Letter Description
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/// 00 M68000 Dn or An r any register
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/// 01 M68000 Dn d data register direct
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/// 02 M68000 An a address register direct
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/// 03 M68000 (An) j address register indirect
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/// 04 M68000 (An)+ o address register indirect with postincrement
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/// 05 M68000 -(An) e address register indirect with predecrement
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/// 06 M68000 (i,An) p address register indirect with displacement
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/// 10 M68000 (i,An,Xn.L) f address register indirect with index and scale = 1
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/// 07 M68000 (i,An,Xn.W) F address register indirect with index and scale = 1
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/// 12 M68020 (i,An,Xn.L,SCALE) g address register indirect with index
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/// 11 M68020 (i,An,Xn.W,SCALE) G address register indirect with index
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/// 14 M68020 ([bd,An],Xn.L,SCALE,od) u memory indirect postindexed mode
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/// 13 M68020 ([bd,An],Xn.W,SCALE,od) U memory indirect postindexed mode
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/// 16 M68020 ([bd,An,Xn.L,SCALE],od) v memory indirect preindexed mode
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/// 15 M68020 ([bd,An,Xn.W,SCALE],od) V memory indirect preindexed mode
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/// 20 M68000 abs.L b absolute long address
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/// 17 M68000 abs.W B absolute short address
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/// 21 M68000 (i,PC) q program counter with displacement
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/// 23 M68000 (i,PC,Xn.L) k program counter with index and scale = 1
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/// 22 M68000 (i,PC,Xn.W) K program counter with index and scale = 1
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/// 25 M68020 (i,PC,Xn.L,SCALE) l program counter with index
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/// 24 M68020 (i,PC,Xn.W,SCALE) L program counter with index
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/// 27 M68020 ([bd,PC],Xn.L,SCALE,od) x program counter memory indirect postindexed mode
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/// 26 M68020 ([bd,PC],Xn.W,SCALE,od) X program counter memory indirect postindexed mode
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/// 31 M68020 ([bd,PC,Xn.L,SCALE],od) y program counter memory indirect preindexed mode
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/// 30 M68020 ([bd,PC,Xn.W,SCALE],od) Y program counter memory indirect preindexed mode
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/// 32 M68000 #immediate i immediate data
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///
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/// NOTE that long form is always lowercase, word variants are capitalized
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///
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/// Operand can be qualified with size where appropriate to force a particular
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/// instruction encoding, e.g.:
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/// (i8,An,Xn.W) f8 1 extension word
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/// (i16,An,Xn.W) f16 2 extension words
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/// (i32,An,Xn.W) f32 3 extension words
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///
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/// Form without size qualifier will adapt to operand size automatically, e.g.:
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/// (i,An,Xn.W) f 1, 2 or 3 extension words
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///
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/// Some forms already imply a particular size of their operands, e.g.:
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/// (i,An) p 1 extension word and i is 16bit
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///
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/// Operand order follows x86 Intel order(destination before source), e.g.:
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/// MOV8df MOVE (4,A0,D0), D1
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///
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/// Number after instruction mnemonics determines the size of the data
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///
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//===----------------------------------------------------------------------===//
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/// ??? Is it possible to use this stuff for disassembling?
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/// NOTE 1: In case of conditional beads(DA, DAReg), cond part is able to
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/// consume any bit, though a more general instructions must be chosen, e.g.
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/// d -> r, a -> r
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//===----------------------------------------------------------------------===//
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// Encoding primitives
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//===----------------------------------------------------------------------===//
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class MxBead<bits<4> type, bit b4 = 0, bit b5 = 0, bit b6 = 0, bit b7 = 0> {
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bits<8> Value = 0b00000000;
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let Value{3-0} = type;
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let Value{4} = b4;
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let Value{5} = b5;
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let Value{6} = b6;
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let Value{7} = b7;
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}
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/// System beads, allow to control beading flow
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def MxBeadTerm : MxBead<0x0, 0, 0, 0, 0>;
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def MxBeadIgnore : MxBead<0x0, 1, 0, 0, 0>;
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/// Add plain bit to the instruction
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class MxBead1Bit <bits<1> b> : MxBead<0x1, b>;
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class MxBead2Bits <bits<2> b> : MxBead<0x2, b{0}, b{1}>;
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class MxBead3Bits <bits<3> b> : MxBead<0x3, b{0}, b{1}, b{2}>;
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class MxBead4Bits <bits<4> b> : MxBead<0x4, b{0}, b{1}, b{2}, b{3}>;
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/// bits<3> o - operand number
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/// bit a - use alternative, used to select index register or
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/// outer displacement/immediate
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/// suffix NP means non-padded
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class MxBeadDAReg <bits<3> o, bit a = 0> : MxBead<0x5, o{0}, o{1}, o{2}, a>;
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class MxBeadDA <bits<3> o, bit a = 0> : MxBead<0x6, o{0}, o{1}, o{2}, a>;
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class MxBeadReg <bits<3> o, bit a = 0> : MxBead<0x7, o{0}, o{1}, o{2}, a>;
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class MxBeadDReg <bits<3> o, bit a = 0> : MxBead<0x8, o{0}, o{1}, o{2}, a>;
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class MxBead8Disp <bits<3> o, bit a = 0> : MxBead<0x9, o{0}, o{1}, o{2}, a>;
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/// Add Immediate to the instruction. 8-bit version is padded with zeros to fit
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/// the word.
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class MxBead8Imm <bits<3> o, bit a = 0> : MxBead<0xA, o{0}, o{1}, o{2}, a>;
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class MxBead16Imm <bits<3> o, bit a = 0> : MxBead<0xB, o{0}, o{1}, o{2}, a>;
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class MxBead32Imm <bits<3> o, bit a = 0> : MxBead<0xC, o{0}, o{1}, o{2}, a>;
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/// Encodes an immediate 0-7(alt. 1-8) into 3 bit field
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class MxBead3Imm <bits<3> o, bit a = 0> : MxBead<0xD, o{0}, o{1}, o{2}, a>;
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class MxEncoding<MxBead n0 = MxBeadTerm, MxBead n1 = MxBeadTerm,
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MxBead n2 = MxBeadTerm, MxBead n3 = MxBeadTerm,
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MxBead n4 = MxBeadTerm, MxBead n5 = MxBeadTerm,
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MxBead n6 = MxBeadTerm, MxBead n7 = MxBeadTerm,
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MxBead n8 = MxBeadTerm, MxBead n9 = MxBeadTerm,
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MxBead n10 = MxBeadTerm, MxBead n11 = MxBeadTerm,
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MxBead n12 = MxBeadTerm, MxBead n13 = MxBeadTerm,
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MxBead n14 = MxBeadTerm, MxBead n15 = MxBeadTerm,
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MxBead n16 = MxBeadTerm, MxBead n17 = MxBeadTerm,
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MxBead n18 = MxBeadTerm, MxBead n19 = MxBeadTerm,
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MxBead n20 = MxBeadTerm, MxBead n21 = MxBeadTerm,
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MxBead n22 = MxBeadTerm, MxBead n23 = MxBeadTerm> {
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bits <192> Value;
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let Value{7-0} = n0.Value;
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let Value{15-8} = n1.Value;
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let Value{23-16} = n2.Value;
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let Value{31-24} = n3.Value;
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let Value{39-32} = n4.Value;
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let Value{47-40} = n5.Value;
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let Value{55-48} = n6.Value;
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let Value{63-56} = n7.Value;
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let Value{71-64} = n8.Value;
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let Value{79-72} = n9.Value;
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let Value{87-80} = n10.Value;
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let Value{95-88} = n11.Value;
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let Value{103-96} = n12.Value;
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let Value{111-104} = n13.Value;
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let Value{119-112} = n14.Value;
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let Value{127-120} = n15.Value;
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let Value{135-128} = n16.Value;
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let Value{143-136} = n17.Value;
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let Value{151-144} = n18.Value;
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let Value{159-152} = n19.Value;
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let Value{167-160} = n20.Value;
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let Value{175-168} = n21.Value;
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let Value{183-176} = n22.Value;
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let Value{191-184} = n23.Value;
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}
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class MxEncFixed<bits<16> value> : MxEncoding {
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let Value{7-0} = MxBead4Bits<value{3-0}>.Value;
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let Value{15-8} = MxBead4Bits<value{7-4}>.Value;
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let Value{23-16} = MxBead4Bits<value{11-8}>.Value;
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let Value{31-24} = MxBead4Bits<value{15-12}>.Value;
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}
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//===----------------------------------------------------------------------===//
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// Encoding composites
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//
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// These must be lowered to MxEncoding by instr specific wrappers
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//
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// HERE BE DRAGONS...
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//===----------------------------------------------------------------------===//
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class MxEncByte<bits<8> value> : MxEncoding {
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MxBead4Bits LO = MxBead4Bits<value{3-0}>;
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MxBead4Bits HI = MxBead4Bits<value{7-4}>;
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}
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def MxEncEmpty : MxEncoding;
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/// M68k Standard Effective Address layout:
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///
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/// :-------------------:
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/// | 5 4 3 | 2 1 0 |
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/// | mode | reg |
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/// :-------------------:
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///
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/// If the EA is a direct register mode, bits 4 and 5 are 0, and the register
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/// number will be encoded in bit 0 - 3. Since the first address register's
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/// (A0) register number is 8, we can easily tell data registers from
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/// address registers by only inspecting bit 3 (i.e. if bit 3 is set, it's an
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/// address register).
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///
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///
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/// But MOVE instruction uses reversed layout for destination EA:
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///
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/// :-------------------:
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/// | 5 4 3 | 2 1 0 |
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/// | reg | mode |
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/// :-------------------:
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///
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/// And this complicates things a bit because the DA bit is now separated from
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/// the register and we have to encode those separately using MxBeadDA<opN>
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///
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class MxEncEA<MxBead reg, MxBead mode, MxBead da = MxBeadIgnore> {
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MxBead Reg = reg;
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MxBead Mode = mode;
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MxBead DA = da;
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}
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// FIXME: Is there a way to factorize the addressing mode suffix (i.e.
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// 'r', 'd', 'a' etc.) and use something like multiclass to replace?
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def MxEncEAr_0: MxEncEA<MxBeadDAReg<0>, MxBead2Bits<0b00>>;
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def MxEncEAd_0: MxEncEA<MxBeadDReg<0>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
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def MxEncEAa_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBead1Bit<1>>;
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def MxEncEAj_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
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def MxEncEAo_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
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def MxEncEAe_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b10>, MxBead1Bit<0>>;
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def MxEncEAp_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b10>, MxBead1Bit<1>>;
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def MxEncEAf_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
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def MxEncEAa_0_reflected : MxEncEA<MxBeadReg<0>, MxBead3Bits<0b001>>;
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def MxEncEAr_0_reflected : MxEncEA<MxBeadReg<0>, MxBead2Bits<0b00>, MxBeadDA<0>>;
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def MxEncEAr_1: MxEncEA<MxBeadDAReg<1>, MxBead2Bits<0b00>>;
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def MxEncEAd_1: MxEncEA<MxBeadDReg<1>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
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def MxEncEAa_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b00>, MxBead1Bit<1>>;
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def MxEncEAj_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
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def MxEncEAo_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
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def MxEncEAe_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b10>, MxBead1Bit<0>>;
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def MxEncEAp_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b10>, MxBead1Bit<1>>;
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def MxEncEAf_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
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def MxEncEAr_2: MxEncEA<MxBeadDAReg<2>, MxBead2Bits<0b00>>;
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def MxEncEAd_2: MxEncEA<MxBeadDReg<2>, MxBead2Bits<0b00>, MxBead1Bit<0>>;
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def MxEncEAa_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b00>, MxBead1Bit<1>>;
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def MxEncEAj_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b01>, MxBead1Bit<0>>;
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def MxEncEAo_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b01>, MxBead1Bit<1>>;
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def MxEncEAe_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b10>, MxBead1Bit<0>>;
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def MxEncEAp_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b10>, MxBead1Bit<1>>;
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def MxEncEAf_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
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def MxEncEAb : MxEncEA<MxBead3Bits<0b001>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
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def MxEncEAq : MxEncEA<MxBead3Bits<0b010>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
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def MxEncEAk : MxEncEA<MxBead3Bits<0b011>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
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def MxEncEAi : MxEncEA<MxBead3Bits<0b100>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
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// Allows you to specify each bit of opcode
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class MxEncOpMode<MxBead b0, MxBead b1 = MxBeadIgnore, MxBead b2 = MxBeadIgnore> {
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MxBead B0 = b0;
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MxBead B1 = b1;
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MxBead B2 = b2;
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}
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// op EA, Dn
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def MxOpMode8dEA : MxEncOpMode<MxBead3Bits<0b000>>;
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def MxOpMode16dEA : MxEncOpMode<MxBead3Bits<0b001>>;
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def MxOpMode32dEA : MxEncOpMode<MxBead3Bits<0b010>>;
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// op EA, An
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def MxOpMode16aEA : MxEncOpMode<MxBead3Bits<0b110>>;
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def MxOpMode32aEA : MxEncOpMode<MxBead3Bits<0b111>>;
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// op EA, Rn
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// As you might noticed this guy is special... Since M68k differentiates
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// between Data and Address registers we required to use different OPMODE codes
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// for Address registers DST operands. One way of dealing with it is to use
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// separate tablegen instructions, but in this case it would force Register
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// Allocator to use specific Register Classes and eventually will lead to
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// superfluous moves. Another approach is to use reg-variadic encoding which will
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// change OPMODE base on Register Class used. Luckily, all the bits that differ go
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// from 0 to 1 and can be encoded with MxBeadDA.
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// Basically, if the register used is of Data type these encodings will be
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// the same as MxOpMode{16,32}dEA above and used with regular instructions(e.g. ADD,
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// SUB), but if the register is of Address type the appropriate bits will flip and
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// the instructions become of *A type(e.g ADDA, SUBA).
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def MxOpMode16rEA : MxEncOpMode<MxBead1Bit<1>, MxBeadDA<0>, MxBead1Bit<0>>;
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def MxOpMode32rEA : MxEncOpMode<MxBeadDA<0>, MxBead1Bit<1>, MxBeadDA<0>>;
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// op Dn, EA
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def MxOpMode8EAd : MxEncOpMode<MxBead3Bits<0b100>>;
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def MxOpMode16EAd : MxEncOpMode<MxBead3Bits<0b101>>;
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def MxOpMode32EAd : MxEncOpMode<MxBead3Bits<0b110>>;
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// Represents two types of extension word:
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// - Imm extension word
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// - Brief extension word
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class MxEncExt<MxBead imm = MxBeadIgnore, MxBead b8 = MxBeadIgnore,
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MxBead scale = MxBeadIgnore, MxBead wl = MxBeadIgnore,
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MxBead daReg = MxBeadIgnore> {
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MxBead Imm = imm;
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MxBead B8 = b8;
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MxBead Scale = scale;
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MxBead WL = wl;
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MxBead DAReg = daReg;
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}
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def MxExtEmpty : MxEncExt;
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// These handle encoding of displacement fields, absolute addresses and
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// immediate values, since encoding for these categories is mainly the same,
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// with exception of some weird immediates.
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def MxExtI8_0 : MxEncExt<MxBead8Imm<0>>;
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def MxExtI16_0 : MxEncExt<MxBead16Imm<0>>;
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def MxExtI32_0 : MxEncExt<MxBead32Imm<0>>;
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def MxExtI8_1 : MxEncExt<MxBead8Imm<1>>;
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def MxExtI16_1 : MxEncExt<MxBead16Imm<1>>;
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def MxExtI32_1 : MxEncExt<MxBead32Imm<1>>;
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def MxExtI8_2 : MxEncExt<MxBead8Imm<2>>;
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def MxExtI16_2 : MxEncExt<MxBead16Imm<2>>;
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def MxExtI32_2 : MxEncExt<MxBead32Imm<2>>;
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// NOTE They are all using Long Xn
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def MxExtBrief_0 : MxEncExt<MxBead8Disp<0>, MxBead1Bit<0b0>,
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MxBead2Bits<0b00>, MxBead1Bit<1>,
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MxBeadDAReg<0, 1>>;
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def MxExtBrief_1 : MxEncExt<MxBead8Disp<1>, MxBead1Bit<0b0>,
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MxBead2Bits<0b00>, MxBead1Bit<1>,
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MxBeadDAReg<1, 1>>;
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def MxExtBrief_2 : MxEncExt<MxBead8Disp<2>, MxBead1Bit<0b0>,
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MxBead2Bits<0b00>, MxBead1Bit<1>,
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MxBeadDAReg<2, 1>>;
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def MxExtBrief_3 : MxEncExt<MxBead8Disp<3>, MxBead1Bit<0b0>,
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MxBead2Bits<0b00>, MxBead1Bit<1>,
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MxBeadDAReg<3, 1>>;
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def MxExtBrief_4 : MxEncExt<MxBead8Disp<4>, MxBead1Bit<0b0>,
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MxBead2Bits<0b00>, MxBead1Bit<1>,
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MxBeadDAReg<4, 1>>;
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class MxEncSize<bits<2> value> : MxBead2Bits<value>;
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def MxEncSize8 : MxEncSize<0b00>;
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def MxEncSize16 : MxEncSize<0b01>;
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def MxEncSize32 : MxEncSize<0b10>;
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def MxEncSize64 : MxEncSize<0b11>;
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// M68k INSTRUCTION. Most instructions specify the location of an operand by
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// using the effective address field in the operation word. The effective address
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// is composed of two 3-bit fields: the mode field and the register field. The
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// value in the mode field selects the different address modes. The register
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// field contains the number of a register. The effective address field may
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// require additional information to fully specify the operand. This additional
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// information, called the effective address extension, is contained in the
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// following word or words and is considered part of the instruction. The
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// effective address modes are grouped into three categories: register direct,
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// memory addressing, and special.
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class MxInst<dag outs, dag ins,
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string asmStr = "",
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list<dag> pattern = [],
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MxEncoding beads = MxEncEmpty,
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InstrItinClass itin = NoItinerary>
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: Instruction {
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let Namespace = "M68k";
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asmStr;
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let Pattern = pattern;
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let Itinerary = itin;
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// Byte stream
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field bits<192> Beads = beads.Value;
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// Number of bytes
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let Size = 0;
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let UseLogicalOperandMappings = 1;
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}
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// M68k PSEUDO INSTRUCTION
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class MxPseudo<dag outs, dag ins, list<dag> pattern = []>
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: MxInst<outs, ins, "; error: this should not be emitted", pattern> {
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let isPseudo = 1;
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}
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