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10839866a1
This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line. This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned. One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU. I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning. Differential Revision: https://reviews.llvm.org/D85165
73 lines
2.6 KiB
C++
73 lines
2.6 KiB
C++
//===-- MSP430MCTargetDesc.cpp - MSP430 Target Descriptions ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides MSP430 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430MCTargetDesc.h"
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#include "MSP430InstPrinter.h"
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#include "MSP430MCAsmInfo.h"
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#include "TargetInfo/MSP430TargetInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "MSP430GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "MSP430GenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "MSP430GenRegisterInfo.inc"
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static MCInstrInfo *createMSP430MCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitMSP430MCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createMSP430MCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitMSP430MCRegisterInfo(X, MSP430::PC);
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return X;
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}
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static MCSubtargetInfo *
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createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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return createMSP430MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
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}
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static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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if (SyntaxVariant == 0)
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return new MSP430InstPrinter(MAI, MII, MRI);
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return nullptr;
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430TargetMC() {
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Target &T = getTheMSP430Target();
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RegisterMCAsmInfo<MSP430MCAsmInfo> X(T);
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TargetRegistry::RegisterMCInstrInfo(T, createMSP430MCInstrInfo);
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TargetRegistry::RegisterMCRegInfo(T, createMSP430MCRegisterInfo);
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TargetRegistry::RegisterMCSubtargetInfo(T, createMSP430MCSubtargetInfo);
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TargetRegistry::RegisterMCInstPrinter(T, createMSP430MCInstPrinter);
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TargetRegistry::RegisterMCCodeEmitter(T, createMSP430MCCodeEmitter);
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TargetRegistry::RegisterMCAsmBackend(T, createMSP430MCAsmBackend);
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TargetRegistry::RegisterObjectTargetStreamer(
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T, createMSP430ObjectTargetStreamer);
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}
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