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1ee52b6300
The GlobalISelEmitter is stricter about matching timm instruction outputs to timm inputs (although in an accidental sort of way that doesn't hit a proper import failure error). Also, apparently no intrinsic patterns were importing since the ID enum declaration was missing.
105 lines
3.2 KiB
C++
105 lines
3.2 KiB
C++
//===-- RISCVInstructionSelector.cpp -----------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the InstructionSelector class for
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/// RISCV.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "RISCVRegisterBankInfo.h"
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#include "RISCVSubtarget.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
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#include "llvm/IR/IntrinsicsRISCV.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "riscv-isel"
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using namespace llvm;
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#include "RISCVGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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namespace {
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class RISCVInstructionSelector : public InstructionSelector {
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public:
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RISCVInstructionSelector(const RISCVTargetMachine &TM,
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const RISCVSubtarget &STI,
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const RISCVRegisterBankInfo &RBI);
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bool select(MachineInstr &I) override;
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static const char *getName() { return DEBUG_TYPE; }
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private:
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bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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const RISCVSubtarget &STI;
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const RISCVInstrInfo &TII;
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const RISCVRegisterInfo &TRI;
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const RISCVRegisterBankInfo &RBI;
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// FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
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// uses "STI." in the code generated by TableGen. We need to unify the name of
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// Subtarget variable.
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const RISCVSubtarget *Subtarget = &STI;
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#define GET_GLOBALISEL_PREDICATES_DECL
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#include "RISCVGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_DECL
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "RISCVGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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};
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} // end anonymous namespace
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#define GET_GLOBALISEL_IMPL
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#include "RISCVGenGlobalISel.inc"
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#undef GET_GLOBALISEL_IMPL
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RISCVInstructionSelector::RISCVInstructionSelector(
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const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
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const RISCVRegisterBankInfo &RBI)
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: InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()),
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TRI(*STI.getRegisterInfo()), RBI(RBI),
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#define GET_GLOBALISEL_PREDICATES_INIT
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#include "RISCVGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_INIT
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#define GET_GLOBALISEL_TEMPORARIES_INIT
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#include "RISCVGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_INIT
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{
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}
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bool RISCVInstructionSelector::select(MachineInstr &I) {
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if (!isPreISelGenericOpcode(I.getOpcode())) {
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// Certain non-generic instructions also need some special handling.
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return true;
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}
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if (selectImpl(I, *CoverageInfo))
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return true;
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return false;
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}
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namespace llvm {
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InstructionSelector *
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createRISCVInstructionSelector(const RISCVTargetMachine &TM,
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RISCVSubtarget &Subtarget,
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RISCVRegisterBankInfo &RBI) {
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return new RISCVInstructionSelector(TM, Subtarget, RBI);
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}
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} // end namespace llvm
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