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0c8a79e78d
Add the scheduling resources for the V extension instructions. Differential Revision: https://reviews.llvm.org/D98002 (cherry picked from commit 63a5ac4e0d969f41bf71785cc3979349a45a2892)
234 lines
11 KiB
TableGen
234 lines
11 KiB
TableGen
//===-- RISCVSchedule.td - RISCV Scheduling Definitions ----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// Define scheduler resources associated with def operands.
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def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
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def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
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def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
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def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
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def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
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def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
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def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
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def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
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def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
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def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I
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def WriteJmp : SchedWrite; // Jump
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def WriteJal : SchedWrite; // Jump and link
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def WriteJalr : SchedWrite; // Jump and link register
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def WriteJmpReg : SchedWrite; // Jump register
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def WriteNop : SchedWrite;
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def WriteLDB : SchedWrite; // Load byte
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def WriteLDH : SchedWrite; // Load half-word
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def WriteLDW : SchedWrite; // Load word
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def WriteLDWU : SchedWrite; // Load word unsigned
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def WriteLDD : SchedWrite; // Load double-word
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def WriteCSR : SchedWrite; // CSR instructions
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def WriteSTB : SchedWrite; // Store byte
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def WriteSTH : SchedWrite; // Store half-word
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def WriteSTW : SchedWrite; // Store word
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def WriteSTD : SchedWrite; // Store double-word
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def WriteAtomicW : SchedWrite; //Atomic memory operation word size
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def WriteAtomicD : SchedWrite; //Atomic memory operation double word size
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def WriteAtomicLDW : SchedWrite; // Atomic load word
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def WriteAtomicLDD : SchedWrite; // Atomic load double word
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def WriteAtomicSTW : SchedWrite; // Atomic store word
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def WriteAtomicSTD : SchedWrite; // Atomic store double word
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def WriteFALU16 : SchedWrite; // FP 16-bit computation
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def WriteFALU32 : SchedWrite; // FP 32-bit computation
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def WriteFALU64 : SchedWrite; // FP 64-bit computation
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def WriteFMul16 : SchedWrite; // 16-bit floating point multiply
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def WriteFMA16 : SchedWrite; // 16-bit floating point fused multiply-add
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def WriteFMul32 : SchedWrite; // 32-bit floating point multiply
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def WriteFMA32 : SchedWrite; // 32-bit floating point fused multiply-add
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def WriteFMul64 : SchedWrite; // 64-bit floating point multiply
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def WriteFMA64 : SchedWrite; // 64-bit floating point fused multiply-add
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def WriteFDiv16 : SchedWrite; // 16-bit floating point divide
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def WriteFDiv32 : SchedWrite; // 32-bit floating point divide
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def WriteFDiv64 : SchedWrite; // 64-bit floating point divide
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def WriteFSqrt16 : SchedWrite; // 16-bit floating point sqrt
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def WriteFSqrt32 : SchedWrite; // 32-bit floating point sqrt
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def WriteFSqrt64 : SchedWrite; // 64-bit floating point sqrt
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// Integer to float conversions
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def WriteFCvtI32ToF16 : SchedWrite;
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def WriteFCvtI32ToF32 : SchedWrite;
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def WriteFCvtI32ToF64 : SchedWrite;
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def WriteFCvtI64ToF16 : SchedWrite; // RV64I only
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def WriteFCvtI64ToF32 : SchedWrite; // RV64I only
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def WriteFCvtI64ToF64 : SchedWrite; // RV64I only
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//Float to integer conversions
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def WriteFCvtF16ToI32 : SchedWrite;
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def WriteFCvtF16ToI64 : SchedWrite; // RV64I only
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def WriteFCvtF32ToI32 : SchedWrite;
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def WriteFCvtF32ToI64 : SchedWrite; // RV64I only
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def WriteFCvtF64ToI32 : SchedWrite;
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def WriteFCvtF64ToI64 : SchedWrite; // RV64I only
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// Float to float conversions
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def WriteFCvtF32ToF64 : SchedWrite;
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def WriteFCvtF64ToF32 : SchedWrite;
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def WriteFCvtF16ToF32 : SchedWrite;
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def WriteFCvtF32ToF16 : SchedWrite;
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def WriteFCvtF16ToF64 : SchedWrite;
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def WriteFCvtF64ToF16 : SchedWrite;
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def WriteFClass16 : SchedWrite; // 16-bit floating point classify
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def WriteFClass32 : SchedWrite; // 32-bit floating point classify
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def WriteFClass64 : SchedWrite; // 64-bit floating point classify
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def WriteFCmp16 : SchedWrite; // 16-bit floating point compare
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def WriteFCmp32 : SchedWrite; // 32-bit floating point compare
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def WriteFCmp64 : SchedWrite; // 64-bit floating point compare
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def WriteFSGNJ16 : SchedWrite; // 16-bit floating point sign-injection
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def WriteFSGNJ32 : SchedWrite; // 32-bit floating point sign-injection
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def WriteFSGNJ64 : SchedWrite; // 64-bit floating point sign-injection
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def WriteFMinMax16 : SchedWrite; // 16-bit floating point min or max
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def WriteFMinMax32 : SchedWrite; // 32-bit floating point min or max
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def WriteFMinMax64 : SchedWrite; // 64-bit floating point min or max
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def WriteFMovF16ToI16 : SchedWrite;
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def WriteFMovI16ToF16 : SchedWrite;
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def WriteFMovF32ToI32 : SchedWrite;
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def WriteFMovI32ToF32 : SchedWrite;
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def WriteFMovF64ToI64 : SchedWrite; // RV64I only
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def WriteFMovI64ToF64 : SchedWrite; // RV64I only
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def WriteFLD16 : SchedWrite; // Floating point sp load
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def WriteFLD32 : SchedWrite; // Floating point sp load
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def WriteFLD64 : SchedWrite; // Floating point dp load
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def WriteFST16 : SchedWrite; // Floating point sp store
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def WriteFST32 : SchedWrite; // Floating point sp store
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def WriteFST64 : SchedWrite; // Floating point dp store
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/// Define scheduler resources associated with use operands.
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def ReadJmp : SchedRead;
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def ReadJalr : SchedRead;
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def ReadCSR : SchedRead;
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def ReadMemBase : SchedRead;
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def ReadFMemBase : SchedRead;
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def ReadStoreData : SchedRead;
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def ReadIALU : SchedRead;
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def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I
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def ReadShiftImm : SchedRead;
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def ReadShiftImm32 : SchedRead; // 32-bit shift by immediate operations on RV64Ix
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def ReadShiftReg : SchedRead;
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def ReadShiftReg32 : SchedRead; // 32-bit shift by register operations on RV64Ix
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def ReadIDiv : SchedRead;
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def ReadIDiv32 : SchedRead;
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def ReadIMul : SchedRead;
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def ReadIMul32 : SchedRead;
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def ReadAtomicWA : SchedRead;
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def ReadAtomicWD : SchedRead;
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def ReadAtomicDA : SchedRead;
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def ReadAtomicDD : SchedRead;
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def ReadAtomicLDW : SchedRead; // Atomic load word
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def ReadAtomicLDD : SchedRead; // Atomic load double word
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def ReadAtomicSTW : SchedRead; // Atomic store word
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def ReadAtomicSTD : SchedRead; // Atomic store double word
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def ReadFALU16 : SchedRead; // FP 16-bit computation
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def ReadFALU32 : SchedRead; // FP 32-bit computation
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def ReadFALU64 : SchedRead; // FP 64-bit computation
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def ReadFMul16 : SchedRead; // 16-bit floating point multiply
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def ReadFMA16 : SchedRead; // 16-bit floating point fused multiply-add
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def ReadFMul32 : SchedRead; // 32-bit floating point multiply
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def ReadFMA32 : SchedRead; // 32-bit floating point fused multiply-add
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def ReadFMul64 : SchedRead; // 64-bit floating point multiply
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def ReadFMA64 : SchedRead; // 64-bit floating point fused multiply-add
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def ReadFDiv16 : SchedRead; // 16-bit floating point divide
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def ReadFDiv32 : SchedRead; // 32-bit floating point divide
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def ReadFDiv64 : SchedRead; // 64-bit floating point divide
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def ReadFSqrt16 : SchedRead; // 16-bit floating point sqrt
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def ReadFSqrt32 : SchedRead; // 32-bit floating point sqrt
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def ReadFSqrt64 : SchedRead; // 64-bit floating point sqrt
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def ReadFCmp16 : SchedRead;
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def ReadFCmp32 : SchedRead;
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def ReadFCmp64 : SchedRead;
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def ReadFSGNJ16 : SchedRead;
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def ReadFSGNJ32 : SchedRead;
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def ReadFSGNJ64 : SchedRead;
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def ReadFMinMax16 : SchedRead;
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def ReadFMinMax32 : SchedRead;
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def ReadFMinMax64 : SchedRead;
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def ReadFCvtF16ToI32 : SchedRead;
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def ReadFCvtF16ToI64 : SchedRead;
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def ReadFCvtF32ToI32 : SchedRead;
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def ReadFCvtF32ToI64 : SchedRead;
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def ReadFCvtF64ToI32 : SchedRead;
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def ReadFCvtF64ToI64 : SchedRead;
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def ReadFCvtI32ToF16 : SchedRead;
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def ReadFCvtI32ToF32 : SchedRead;
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def ReadFCvtI32ToF64 : SchedRead;
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def ReadFCvtI64ToF16 : SchedRead;
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def ReadFCvtI64ToF32 : SchedRead;
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def ReadFCvtI64ToF64 : SchedRead;
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def ReadFMovF16ToI16 : SchedRead;
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def ReadFMovI16ToF16 : SchedRead;
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def ReadFMovF32ToI32 : SchedRead;
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def ReadFMovI32ToF32 : SchedRead;
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def ReadFMovF64ToI64 : SchedRead;
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def ReadFMovI64ToF64 : SchedRead;
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def ReadFCvtF32ToF64 : SchedRead;
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def ReadFCvtF64ToF32 : SchedRead;
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def ReadFCvtF16ToF32 : SchedRead;
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def ReadFCvtF32ToF16 : SchedRead;
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def ReadFCvtF16ToF64 : SchedRead;
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def ReadFCvtF64ToF16 : SchedRead;
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def ReadFClass16 : SchedRead;
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def ReadFClass32 : SchedRead;
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def ReadFClass64 : SchedRead;
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multiclass UnsupportedSchedZfh {
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let Unsupported = true in {
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def : WriteRes<WriteFALU16, []>;
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def : WriteRes<WriteFClass16, []>;
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def : WriteRes<WriteFCvtF16ToF64, []>;
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def : WriteRes<WriteFCvtF64ToF16, []>;
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def : WriteRes<WriteFCvtI64ToF16, []>;
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def : WriteRes<WriteFCvtF32ToF16, []>;
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def : WriteRes<WriteFCvtI32ToF16, []>;
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def : WriteRes<WriteFCvtF16ToI64, []>;
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def : WriteRes<WriteFCvtF16ToF32, []>;
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def : WriteRes<WriteFCvtF16ToI32, []>;
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def : WriteRes<WriteFDiv16, []>;
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def : WriteRes<WriteFCmp16, []>;
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def : WriteRes<WriteFLD16, []>;
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def : WriteRes<WriteFMA16, []>;
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def : WriteRes<WriteFMinMax16, []>;
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def : WriteRes<WriteFMul16, []>;
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def : WriteRes<WriteFMovI16ToF16, []>;
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def : WriteRes<WriteFMovF16ToI16, []>;
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def : WriteRes<WriteFSGNJ16, []>;
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def : WriteRes<WriteFST16, []>;
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def : WriteRes<WriteFSqrt16, []>;
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def : ReadAdvance<ReadFALU16, 0>;
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def : ReadAdvance<ReadFClass16, 0>;
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def : ReadAdvance<ReadFCvtF16ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF16, 0>;
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def : ReadAdvance<ReadFCvtI64ToF16, 0>;
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def : ReadAdvance<ReadFCvtF32ToF16, 0>;
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def : ReadAdvance<ReadFCvtI32ToF16, 0>;
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def : ReadAdvance<ReadFCvtF16ToI64, 0>;
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def : ReadAdvance<ReadFCvtF16ToF32, 0>;
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def : ReadAdvance<ReadFCvtF16ToI32, 0>;
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def : ReadAdvance<ReadFDiv16, 0>;
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def : ReadAdvance<ReadFCmp16, 0>;
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def : ReadAdvance<ReadFMA16, 0>;
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def : ReadAdvance<ReadFMinMax16, 0>;
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def : ReadAdvance<ReadFMul16, 0>;
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def : ReadAdvance<ReadFMovI16ToF16, 0>;
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def : ReadAdvance<ReadFMovF16ToI16, 0>;
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def : ReadAdvance<ReadFSGNJ16, 0>;
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def : ReadAdvance<ReadFSqrt16, 0>;
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} // Unsupported = true
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}
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// Include the scheduler resources for other instruction extensions.
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include "RISCVScheduleB.td"
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include "RISCVScheduleV.td"
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