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4f172e6801
Indirect sibling calls need to use %r1 to hold the target address. This is currently hard-coded in many places. This is not only unnecessary, but makes future changes in this area difficult. This patch now encodes the target address as operand without hard coding a register in most places throughout the MI back-end. Code generation still always uses %r1, but this is now decided solely in one place in SystemZTargetLowering::LowerCall. NFC intended.
753 lines
26 KiB
C++
753 lines
26 KiB
C++
//===-- SystemZElimCompare.cpp - Eliminate comparison instructions --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass:
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// (1) tries to remove compares if CC already contains the required information
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// (2) fuses compares and branches into COMPARE AND BRANCH instructions
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZTargetMachine.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "systemz-elim-compare"
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STATISTIC(BranchOnCounts, "Number of branch-on-count instructions");
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STATISTIC(LoadAndTraps, "Number of load-and-trap instructions");
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STATISTIC(EliminatedComparisons, "Number of eliminated comparisons");
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STATISTIC(FusedComparisons, "Number of fused compare-and-branch instructions");
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namespace {
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// Represents the references to a particular register in one or more
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// instructions.
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struct Reference {
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Reference() = default;
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Reference &operator|=(const Reference &Other) {
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Def |= Other.Def;
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Use |= Other.Use;
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return *this;
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}
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explicit operator bool() const { return Def || Use; }
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// True if the register is defined or used in some form, either directly or
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// via a sub- or super-register.
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bool Def = false;
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bool Use = false;
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};
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class SystemZElimCompare : public MachineFunctionPass {
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public:
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static char ID;
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SystemZElimCompare(const SystemZTargetMachine &tm)
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: MachineFunctionPass(ID) {}
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StringRef getPassName() const override {
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return "SystemZ Comparison Elimination";
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}
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bool processBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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Reference getRegReferences(MachineInstr &MI, unsigned Reg);
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bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers);
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bool convertToLoadAndTrap(MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers);
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bool convertToLoadAndTest(MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers);
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bool convertToLogical(MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers);
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bool adjustCCMasksForInstr(MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers,
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unsigned ConvOpc = 0);
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bool optimizeCompareZero(MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers);
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bool fuseCompareOperations(MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers);
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const SystemZInstrInfo *TII = nullptr;
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const TargetRegisterInfo *TRI = nullptr;
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};
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char SystemZElimCompare::ID = 0;
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} // end anonymous namespace
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// Returns true if MI is an instruction whose output equals the value in Reg.
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static bool preservesValueOf(MachineInstr &MI, unsigned Reg) {
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switch (MI.getOpcode()) {
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case SystemZ::LR:
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case SystemZ::LGR:
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case SystemZ::LGFR:
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case SystemZ::LTR:
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case SystemZ::LTGR:
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case SystemZ::LTGFR:
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case SystemZ::LER:
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case SystemZ::LDR:
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case SystemZ::LXR:
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case SystemZ::LTEBR:
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case SystemZ::LTDBR:
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case SystemZ::LTXBR:
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if (MI.getOperand(1).getReg() == Reg)
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return true;
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}
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return false;
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}
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// Return true if any CC result of MI would (perhaps after conversion)
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// reflect the value of Reg.
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static bool resultTests(MachineInstr &MI, unsigned Reg) {
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if (MI.getNumOperands() > 0 && MI.getOperand(0).isReg() &&
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MI.getOperand(0).isDef() && MI.getOperand(0).getReg() == Reg)
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return true;
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return (preservesValueOf(MI, Reg));
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}
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// Describe the references to Reg or any of its aliases in MI.
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Reference SystemZElimCompare::getRegReferences(MachineInstr &MI, unsigned Reg) {
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Reference Ref;
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if (MI.isDebugInstr())
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return Ref;
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for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = MI.getOperand(I);
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if (MO.isReg()) {
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if (Register MOReg = MO.getReg()) {
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if (TRI->regsOverlap(MOReg, Reg)) {
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if (MO.isUse())
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Ref.Use = true;
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else if (MO.isDef())
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Ref.Def = true;
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}
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}
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}
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}
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return Ref;
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}
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// Return true if this is a load and test which can be optimized the
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// same way as compare instruction.
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static bool isLoadAndTestAsCmp(MachineInstr &MI) {
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// If we during isel used a load-and-test as a compare with 0, the
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// def operand is dead.
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return (MI.getOpcode() == SystemZ::LTEBR ||
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MI.getOpcode() == SystemZ::LTDBR ||
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MI.getOpcode() == SystemZ::LTXBR) &&
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MI.getOperand(0).isDead();
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}
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// Return the source register of Compare, which is the unknown value
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// being tested.
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static unsigned getCompareSourceReg(MachineInstr &Compare) {
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unsigned reg = 0;
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if (Compare.isCompare())
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reg = Compare.getOperand(0).getReg();
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else if (isLoadAndTestAsCmp(Compare))
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reg = Compare.getOperand(1).getReg();
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assert(reg);
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return reg;
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}
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// Compare compares the result of MI against zero. If MI is an addition
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// of -1 and if CCUsers is a single branch on nonzero, eliminate the addition
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// and convert the branch to a BRCT(G) or BRCTH. Return true on success.
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bool SystemZElimCompare::convertToBRCT(
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MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers) {
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// Check whether we have an addition of -1.
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unsigned Opcode = MI.getOpcode();
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unsigned BRCT;
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if (Opcode == SystemZ::AHI)
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BRCT = SystemZ::BRCT;
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else if (Opcode == SystemZ::AGHI)
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BRCT = SystemZ::BRCTG;
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else if (Opcode == SystemZ::AIH)
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BRCT = SystemZ::BRCTH;
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else
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return false;
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if (MI.getOperand(2).getImm() != -1)
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return false;
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// Check whether we have a single JLH.
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if (CCUsers.size() != 1)
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return false;
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MachineInstr *Branch = CCUsers[0];
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if (Branch->getOpcode() != SystemZ::BRC ||
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Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP ||
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Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_NE)
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return false;
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// We already know that there are no references to the register between
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// MI and Compare. Make sure that there are also no references between
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// Compare and Branch.
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unsigned SrcReg = getCompareSourceReg(Compare);
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MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
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for (++MBBI; MBBI != MBBE; ++MBBI)
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if (getRegReferences(*MBBI, SrcReg))
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return false;
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// The transformation is OK. Rebuild Branch as a BRCT(G) or BRCTH.
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MachineOperand Target(Branch->getOperand(2));
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while (Branch->getNumOperands())
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Branch->RemoveOperand(0);
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Branch->setDesc(TII->get(BRCT));
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MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
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MIB.add(MI.getOperand(0)).add(MI.getOperand(1)).add(Target);
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// Add a CC def to BRCT(G), since we may have to split them again if the
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// branch displacement overflows. BRCTH has a 32-bit displacement, so
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// this is not necessary there.
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if (BRCT != SystemZ::BRCTH)
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MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
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MI.eraseFromParent();
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return true;
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}
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// Compare compares the result of MI against zero. If MI is a suitable load
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// instruction and if CCUsers is a single conditional trap on zero, eliminate
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// the load and convert the branch to a load-and-trap. Return true on success.
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bool SystemZElimCompare::convertToLoadAndTrap(
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MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers) {
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unsigned LATOpcode = TII->getLoadAndTrap(MI.getOpcode());
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if (!LATOpcode)
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return false;
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// Check whether we have a single CondTrap that traps on zero.
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if (CCUsers.size() != 1)
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return false;
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MachineInstr *Branch = CCUsers[0];
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if (Branch->getOpcode() != SystemZ::CondTrap ||
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Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP ||
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Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_EQ)
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return false;
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// We already know that there are no references to the register between
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// MI and Compare. Make sure that there are also no references between
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// Compare and Branch.
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unsigned SrcReg = getCompareSourceReg(Compare);
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MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
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for (++MBBI; MBBI != MBBE; ++MBBI)
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if (getRegReferences(*MBBI, SrcReg))
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return false;
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// The transformation is OK. Rebuild Branch as a load-and-trap.
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while (Branch->getNumOperands())
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Branch->RemoveOperand(0);
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Branch->setDesc(TII->get(LATOpcode));
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MachineInstrBuilder(*Branch->getParent()->getParent(), Branch)
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.add(MI.getOperand(0))
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.add(MI.getOperand(1))
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.add(MI.getOperand(2))
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.add(MI.getOperand(3));
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MI.eraseFromParent();
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return true;
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}
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// If MI is a load instruction, try to convert it into a LOAD AND TEST.
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// Return true on success.
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bool SystemZElimCompare::convertToLoadAndTest(
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MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers) {
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// Try to adjust CC masks for the LOAD AND TEST opcode that could replace MI.
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unsigned Opcode = TII->getLoadAndTest(MI.getOpcode());
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if (!Opcode || !adjustCCMasksForInstr(MI, Compare, CCUsers, Opcode))
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return false;
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// Rebuild to get the CC operand in the right place.
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auto MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(Opcode));
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for (const auto &MO : MI.operands())
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MIB.add(MO);
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MIB.setMemRefs(MI.memoperands());
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MI.eraseFromParent();
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// Mark instruction as not raising an FP exception if applicable. We already
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// verified earlier that this move is valid.
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if (!Compare.mayRaiseFPException())
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MIB.setMIFlag(MachineInstr::MIFlag::NoFPExcept);
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return true;
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}
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// See if MI is an instruction with an equivalent "logical" opcode that can
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// be used and replace MI. This is useful for EQ/NE comparisons where the
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// "nsw" flag is missing since the "logical" opcode always sets CC to reflect
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// the result being zero or non-zero.
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bool SystemZElimCompare::convertToLogical(
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MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers) {
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unsigned ConvOpc = 0;
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switch (MI.getOpcode()) {
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case SystemZ::AR: ConvOpc = SystemZ::ALR; break;
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case SystemZ::ARK: ConvOpc = SystemZ::ALRK; break;
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case SystemZ::AGR: ConvOpc = SystemZ::ALGR; break;
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case SystemZ::AGRK: ConvOpc = SystemZ::ALGRK; break;
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case SystemZ::A: ConvOpc = SystemZ::AL; break;
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case SystemZ::AY: ConvOpc = SystemZ::ALY; break;
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case SystemZ::AG: ConvOpc = SystemZ::ALG; break;
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default: break;
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}
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if (!ConvOpc || !adjustCCMasksForInstr(MI, Compare, CCUsers, ConvOpc))
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return false;
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// Operands should be identical, so just change the opcode and remove the
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// dead flag on CC.
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MI.setDesc(TII->get(ConvOpc));
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MI.clearRegisterDeads(SystemZ::CC);
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return true;
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}
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#ifndef NDEBUG
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static bool isAddWithImmediate(unsigned Opcode) {
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switch(Opcode) {
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case SystemZ::AHI:
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case SystemZ::AHIK:
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case SystemZ::AGHI:
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case SystemZ::AGHIK:
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case SystemZ::AFI:
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case SystemZ::AIH:
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case SystemZ::AGFI:
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return true;
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default: break;
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}
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return false;
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}
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#endif
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// The CC users in CCUsers are testing the result of a comparison of some
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// value X against zero and we know that any CC value produced by MI would
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// also reflect the value of X. ConvOpc may be used to pass the transfomed
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// opcode MI will have if this succeeds. Try to adjust CCUsers so that they
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// test the result of MI directly, returning true on success. Leave
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// everything unchanged on failure.
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bool SystemZElimCompare::adjustCCMasksForInstr(
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MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers,
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unsigned ConvOpc) {
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unsigned CompareFlags = Compare.getDesc().TSFlags;
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unsigned CompareCCValues = SystemZII::getCCValues(CompareFlags);
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int Opcode = (ConvOpc ? ConvOpc : MI.getOpcode());
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const MCInstrDesc &Desc = TII->get(Opcode);
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unsigned MIFlags = Desc.TSFlags;
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// If Compare may raise an FP exception, we can only eliminate it
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// if MI itself would have already raised the exception.
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if (Compare.mayRaiseFPException()) {
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// If the caller will change MI to use ConvOpc, only test whether
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// ConvOpc is suitable; it is on the caller to set the MI flag.
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if (ConvOpc && !Desc.mayRaiseFPException())
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return false;
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// If the caller will not change MI, we test the MI flag here.
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if (!ConvOpc && !MI.mayRaiseFPException())
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return false;
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}
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// See which compare-style condition codes are available.
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unsigned CCValues = SystemZII::getCCValues(MIFlags);
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unsigned ReusableCCMask = CCValues;
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// For unsigned comparisons with zero, only equality makes sense.
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if (CompareFlags & SystemZII::IsLogical)
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ReusableCCMask &= SystemZ::CCMASK_CMP_EQ;
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unsigned OFImplies = 0;
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bool LogicalMI = false;
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bool MIEquivalentToCmp = false;
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if (MI.getFlag(MachineInstr::NoSWrap) &&
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(MIFlags & SystemZII::CCIfNoSignedWrap)) {
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// If MI has the NSW flag set in combination with the
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// SystemZII::CCIfNoSignedWrap flag, all CCValues are valid.
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}
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else if ((MIFlags & SystemZII::CCIfNoSignedWrap) &&
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MI.getOperand(2).isImm()) {
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// Signed addition of immediate. If adding a positive immediate
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// overflows, the result must be less than zero. If adding a negative
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// immediate overflows, the result must be larger than zero (except in
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// the special case of adding the minimum value of the result range, in
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// which case we cannot predict whether the result is larger than or
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// equal to zero).
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assert(isAddWithImmediate(Opcode) && "Expected an add with immediate.");
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assert(!MI.mayLoadOrStore() && "Expected an immediate term.");
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int64_t RHS = MI.getOperand(2).getImm();
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if (SystemZ::GRX32BitRegClass.contains(MI.getOperand(0).getReg()) &&
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RHS == INT32_MIN)
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return false;
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OFImplies = (RHS > 0 ? SystemZ::CCMASK_CMP_LT : SystemZ::CCMASK_CMP_GT);
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}
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else if ((MIFlags & SystemZII::IsLogical) && CCValues) {
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// Use CCMASK_CMP_EQ to match with CCUsers. On success CCMask:s will be
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// converted to CCMASK_LOGICAL_ZERO or CCMASK_LOGICAL_NONZERO.
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LogicalMI = true;
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ReusableCCMask = SystemZ::CCMASK_CMP_EQ;
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}
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else {
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ReusableCCMask &= SystemZII::getCompareZeroCCMask(MIFlags);
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assert((ReusableCCMask & ~CCValues) == 0 && "Invalid CCValues");
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MIEquivalentToCmp =
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ReusableCCMask == CCValues && CCValues == CompareCCValues;
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}
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if (ReusableCCMask == 0)
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return false;
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if (!MIEquivalentToCmp) {
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// Now check whether these flags are enough for all users.
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SmallVector<MachineOperand *, 4> AlterMasks;
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for (unsigned int I = 0, E = CCUsers.size(); I != E; ++I) {
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MachineInstr *CCUserMI = CCUsers[I];
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// Fail if this isn't a use of CC that we understand.
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unsigned Flags = CCUserMI->getDesc().TSFlags;
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unsigned FirstOpNum;
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if (Flags & SystemZII::CCMaskFirst)
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FirstOpNum = 0;
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else if (Flags & SystemZII::CCMaskLast)
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FirstOpNum = CCUserMI->getNumExplicitOperands() - 2;
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else
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return false;
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// Check whether the instruction predicate treats all CC values
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// outside of ReusableCCMask in the same way. In that case it
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// doesn't matter what those CC values mean.
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unsigned CCValid = CCUserMI->getOperand(FirstOpNum).getImm();
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unsigned CCMask = CCUserMI->getOperand(FirstOpNum + 1).getImm();
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assert(CCValid == CompareCCValues && (CCMask & ~CCValid) == 0 &&
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"Corrupt CC operands of CCUser.");
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unsigned OutValid = ~ReusableCCMask & CCValid;
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unsigned OutMask = ~ReusableCCMask & CCMask;
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if (OutMask != 0 && OutMask != OutValid)
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return false;
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AlterMasks.push_back(&CCUserMI->getOperand(FirstOpNum));
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AlterMasks.push_back(&CCUserMI->getOperand(FirstOpNum + 1));
|
|
}
|
|
|
|
// All users are OK. Adjust the masks for MI.
|
|
for (unsigned I = 0, E = AlterMasks.size(); I != E; I += 2) {
|
|
AlterMasks[I]->setImm(CCValues);
|
|
unsigned CCMask = AlterMasks[I + 1]->getImm();
|
|
if (LogicalMI) {
|
|
// Translate the CCMask into its "logical" value.
|
|
CCMask = (CCMask == SystemZ::CCMASK_CMP_EQ ?
|
|
SystemZ::CCMASK_LOGICAL_ZERO : SystemZ::CCMASK_LOGICAL_NONZERO);
|
|
CCMask &= CCValues; // Logical subtracts never set CC=0.
|
|
} else {
|
|
if (CCMask & ~ReusableCCMask)
|
|
CCMask = (CCMask & ReusableCCMask) | (CCValues & ~ReusableCCMask);
|
|
CCMask |= (CCMask & OFImplies) ? SystemZ::CCMASK_ARITH_OVERFLOW : 0;
|
|
}
|
|
AlterMasks[I + 1]->setImm(CCMask);
|
|
}
|
|
}
|
|
|
|
// CC is now live after MI.
|
|
if (!ConvOpc)
|
|
MI.clearRegisterDeads(SystemZ::CC);
|
|
|
|
// Check if MI lies before Compare.
|
|
bool BeforeCmp = false;
|
|
MachineBasicBlock::iterator MBBI = MI, MBBE = MI.getParent()->end();
|
|
for (++MBBI; MBBI != MBBE; ++MBBI)
|
|
if (MBBI == Compare) {
|
|
BeforeCmp = true;
|
|
break;
|
|
}
|
|
|
|
// Clear any intervening kills of CC.
|
|
if (BeforeCmp) {
|
|
MachineBasicBlock::iterator MBBI = MI, MBBE = Compare;
|
|
for (++MBBI; MBBI != MBBE; ++MBBI)
|
|
MBBI->clearRegisterKills(SystemZ::CC, TRI);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
// Return true if Compare is a comparison against zero.
|
|
static bool isCompareZero(MachineInstr &Compare) {
|
|
switch (Compare.getOpcode()) {
|
|
case SystemZ::LTEBRCompare:
|
|
case SystemZ::LTDBRCompare:
|
|
case SystemZ::LTXBRCompare:
|
|
return true;
|
|
|
|
default:
|
|
if (isLoadAndTestAsCmp(Compare))
|
|
return true;
|
|
return Compare.getNumExplicitOperands() == 2 &&
|
|
Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0;
|
|
}
|
|
}
|
|
|
|
// Try to optimize cases where comparison instruction Compare is testing
|
|
// a value against zero. Return true on success and if Compare should be
|
|
// deleted as dead. CCUsers is the list of instructions that use the CC
|
|
// value produced by Compare.
|
|
bool SystemZElimCompare::optimizeCompareZero(
|
|
MachineInstr &Compare, SmallVectorImpl<MachineInstr *> &CCUsers) {
|
|
if (!isCompareZero(Compare))
|
|
return false;
|
|
|
|
// Search back for CC results that are based on the first operand.
|
|
unsigned SrcReg = getCompareSourceReg(Compare);
|
|
MachineBasicBlock &MBB = *Compare.getParent();
|
|
Reference CCRefs;
|
|
Reference SrcRefs;
|
|
for (MachineBasicBlock::reverse_iterator MBBI =
|
|
std::next(MachineBasicBlock::reverse_iterator(&Compare)),
|
|
MBBE = MBB.rend(); MBBI != MBBE;) {
|
|
MachineInstr &MI = *MBBI++;
|
|
if (resultTests(MI, SrcReg)) {
|
|
// Try to remove both MI and Compare by converting a branch to BRCT(G).
|
|
// or a load-and-trap instruction. We don't care in this case whether
|
|
// CC is modified between MI and Compare.
|
|
if (!CCRefs.Use && !SrcRefs) {
|
|
if (convertToBRCT(MI, Compare, CCUsers)) {
|
|
BranchOnCounts += 1;
|
|
return true;
|
|
}
|
|
if (convertToLoadAndTrap(MI, Compare, CCUsers)) {
|
|
LoadAndTraps += 1;
|
|
return true;
|
|
}
|
|
}
|
|
// Try to eliminate Compare by reusing a CC result from MI.
|
|
if ((!CCRefs && convertToLoadAndTest(MI, Compare, CCUsers)) ||
|
|
(!CCRefs.Def &&
|
|
(adjustCCMasksForInstr(MI, Compare, CCUsers) ||
|
|
convertToLogical(MI, Compare, CCUsers)))) {
|
|
EliminatedComparisons += 1;
|
|
return true;
|
|
}
|
|
}
|
|
SrcRefs |= getRegReferences(MI, SrcReg);
|
|
if (SrcRefs.Def)
|
|
break;
|
|
CCRefs |= getRegReferences(MI, SystemZ::CC);
|
|
if (CCRefs.Use && CCRefs.Def)
|
|
break;
|
|
// Eliminating a Compare that may raise an FP exception will move
|
|
// raising the exception to some earlier MI. We cannot do this if
|
|
// there is anything in between that might change exception flags.
|
|
if (Compare.mayRaiseFPException() &&
|
|
(MI.isCall() || MI.hasUnmodeledSideEffects()))
|
|
break;
|
|
}
|
|
|
|
// Also do a forward search to handle cases where an instruction after the
|
|
// compare can be converted, like
|
|
// LTEBRCompare %f0s, %f0s; %f2s = LER %f0s => LTEBRCompare %f2s, %f0s
|
|
for (MachineBasicBlock::iterator MBBI =
|
|
std::next(MachineBasicBlock::iterator(&Compare)), MBBE = MBB.end();
|
|
MBBI != MBBE;) {
|
|
MachineInstr &MI = *MBBI++;
|
|
if (preservesValueOf(MI, SrcReg)) {
|
|
// Try to eliminate Compare by reusing a CC result from MI.
|
|
if (convertToLoadAndTest(MI, Compare, CCUsers)) {
|
|
EliminatedComparisons += 1;
|
|
return true;
|
|
}
|
|
}
|
|
if (getRegReferences(MI, SrcReg).Def)
|
|
return false;
|
|
if (getRegReferences(MI, SystemZ::CC))
|
|
return false;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
// Try to fuse comparison instruction Compare into a later branch.
|
|
// Return true on success and if Compare is therefore redundant.
|
|
bool SystemZElimCompare::fuseCompareOperations(
|
|
MachineInstr &Compare, SmallVectorImpl<MachineInstr *> &CCUsers) {
|
|
// See whether we have a single branch with which to fuse.
|
|
if (CCUsers.size() != 1)
|
|
return false;
|
|
MachineInstr *Branch = CCUsers[0];
|
|
SystemZII::FusedCompareType Type;
|
|
switch (Branch->getOpcode()) {
|
|
case SystemZ::BRC:
|
|
Type = SystemZII::CompareAndBranch;
|
|
break;
|
|
case SystemZ::CondReturn:
|
|
Type = SystemZII::CompareAndReturn;
|
|
break;
|
|
case SystemZ::CallBCR:
|
|
Type = SystemZII::CompareAndSibcall;
|
|
break;
|
|
case SystemZ::CondTrap:
|
|
Type = SystemZII::CompareAndTrap;
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
// See whether we have a comparison that can be fused.
|
|
unsigned FusedOpcode =
|
|
TII->getFusedCompare(Compare.getOpcode(), Type, &Compare);
|
|
if (!FusedOpcode)
|
|
return false;
|
|
|
|
// Make sure that the operands are available at the branch.
|
|
// SrcReg2 is the register if the source operand is a register,
|
|
// 0 if the source operand is immediate, and the base register
|
|
// if the source operand is memory (index is not supported).
|
|
Register SrcReg = Compare.getOperand(0).getReg();
|
|
Register SrcReg2 =
|
|
Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : Register();
|
|
MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
|
|
for (++MBBI; MBBI != MBBE; ++MBBI)
|
|
if (MBBI->modifiesRegister(SrcReg, TRI) ||
|
|
(SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
|
|
return false;
|
|
|
|
// Read the branch mask, target (if applicable), regmask (if applicable).
|
|
MachineOperand CCMask(MBBI->getOperand(1));
|
|
assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 &&
|
|
"Invalid condition-code mask for integer comparison");
|
|
// This is only valid for CompareAndBranch and CompareAndSibcall.
|
|
MachineOperand Target(MBBI->getOperand(
|
|
(Type == SystemZII::CompareAndBranch ||
|
|
Type == SystemZII::CompareAndSibcall) ? 2 : 0));
|
|
const uint32_t *RegMask;
|
|
if (Type == SystemZII::CompareAndSibcall)
|
|
RegMask = MBBI->getOperand(3).getRegMask();
|
|
|
|
// Clear out all current operands.
|
|
int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
|
|
assert(CCUse >= 0 && "BRC/BCR must use CC");
|
|
Branch->RemoveOperand(CCUse);
|
|
// Remove regmask (sibcall).
|
|
if (Type == SystemZII::CompareAndSibcall)
|
|
Branch->RemoveOperand(3);
|
|
// Remove target (branch or sibcall).
|
|
if (Type == SystemZII::CompareAndBranch ||
|
|
Type == SystemZII::CompareAndSibcall)
|
|
Branch->RemoveOperand(2);
|
|
Branch->RemoveOperand(1);
|
|
Branch->RemoveOperand(0);
|
|
|
|
// Rebuild Branch as a fused compare and branch.
|
|
// SrcNOps is the number of MI operands of the compare instruction
|
|
// that we need to copy over.
|
|
unsigned SrcNOps = 2;
|
|
if (FusedOpcode == SystemZ::CLT || FusedOpcode == SystemZ::CLGT)
|
|
SrcNOps = 3;
|
|
Branch->setDesc(TII->get(FusedOpcode));
|
|
MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
|
|
for (unsigned I = 0; I < SrcNOps; I++)
|
|
MIB.add(Compare.getOperand(I));
|
|
MIB.add(CCMask);
|
|
|
|
if (Type == SystemZII::CompareAndBranch) {
|
|
// Only conditional branches define CC, as they may be converted back
|
|
// to a non-fused branch because of a long displacement. Conditional
|
|
// returns don't have that problem.
|
|
MIB.add(Target).addReg(SystemZ::CC,
|
|
RegState::ImplicitDefine | RegState::Dead);
|
|
}
|
|
|
|
if (Type == SystemZII::CompareAndSibcall) {
|
|
MIB.add(Target);
|
|
MIB.addRegMask(RegMask);
|
|
}
|
|
|
|
// Clear any intervening kills of SrcReg and SrcReg2.
|
|
MBBI = Compare;
|
|
for (++MBBI; MBBI != MBBE; ++MBBI) {
|
|
MBBI->clearRegisterKills(SrcReg, TRI);
|
|
if (SrcReg2)
|
|
MBBI->clearRegisterKills(SrcReg2, TRI);
|
|
}
|
|
FusedComparisons += 1;
|
|
return true;
|
|
}
|
|
|
|
// Process all comparison instructions in MBB. Return true if something
|
|
// changed.
|
|
bool SystemZElimCompare::processBlock(MachineBasicBlock &MBB) {
|
|
bool Changed = false;
|
|
|
|
// Walk backwards through the block looking for comparisons, recording
|
|
// all CC users as we go. The subroutines can delete Compare and
|
|
// instructions before it.
|
|
LivePhysRegs LiveRegs(*TRI);
|
|
LiveRegs.addLiveOuts(MBB);
|
|
bool CompleteCCUsers = !LiveRegs.contains(SystemZ::CC);
|
|
SmallVector<MachineInstr *, 4> CCUsers;
|
|
MachineBasicBlock::iterator MBBI = MBB.end();
|
|
while (MBBI != MBB.begin()) {
|
|
MachineInstr &MI = *--MBBI;
|
|
if (CompleteCCUsers && (MI.isCompare() || isLoadAndTestAsCmp(MI)) &&
|
|
(optimizeCompareZero(MI, CCUsers) ||
|
|
fuseCompareOperations(MI, CCUsers))) {
|
|
++MBBI;
|
|
MI.eraseFromParent();
|
|
Changed = true;
|
|
CCUsers.clear();
|
|
continue;
|
|
}
|
|
|
|
if (MI.definesRegister(SystemZ::CC)) {
|
|
CCUsers.clear();
|
|
CompleteCCUsers = true;
|
|
}
|
|
if (MI.readsRegister(SystemZ::CC) && CompleteCCUsers)
|
|
CCUsers.push_back(&MI);
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
bool SystemZElimCompare::runOnMachineFunction(MachineFunction &F) {
|
|
if (skipFunction(F.getFunction()))
|
|
return false;
|
|
|
|
TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
|
|
TRI = &TII->getRegisterInfo();
|
|
|
|
bool Changed = false;
|
|
for (auto &MBB : F)
|
|
Changed |= processBlock(MBB);
|
|
|
|
return Changed;
|
|
}
|
|
|
|
FunctionPass *llvm::createSystemZElimComparePass(SystemZTargetMachine &TM) {
|
|
return new SystemZElimCompare(TM);
|
|
}
|