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There were not properly checked before `[TableGen] Improve handling of template arguments`.
92 lines
3.4 KiB
TableGen
92 lines
3.4 KiB
TableGen
//===-- VEInstrPatternsVec.td - VEC_-type SDNodes and isel for VE Target --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the VEC_* prefixed intermediate SDNodes and their
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// isel patterns.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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multiclass vbrd_elem32<ValueType v32, ValueType s32, SDPatternOperator ImmOp,
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SDNodeXForm ImmCast, OutPatFrag SuperRegCast> {
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// VBRDil
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def : Pat<(v32 (vec_broadcast (s32 ImmOp:$sy), i32:$vl)),
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(VBRDil (ImmCast $sy), i32:$vl)>;
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// VBRDrl
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def : Pat<(v32 (vec_broadcast s32:$sy, i32:$vl)),
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(VBRDrl (SuperRegCast $sy), i32:$vl)>;
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}
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multiclass vbrd_elem64<ValueType v64, ValueType s64,
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SDPatternOperator ImmOp, SDNodeXForm ImmCast> {
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// VBRDil
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def : Pat<(v64 (vec_broadcast (s64 ImmOp:$sy), i32:$vl)),
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(VBRDil (ImmCast $sy), i32:$vl)>;
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// VBRDrl
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def : Pat<(v64 (vec_broadcast s64:$sy, i32:$vl)),
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(VBRDrl s64:$sy, i32:$vl)>;
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}
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multiclass extract_insert_elem32<ValueType v32, ValueType s32,
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OutPatFrag SubRegCast,
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OutPatFrag SuperRegCast> {
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// LVSvi
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def: Pat<(s32 (extractelt v32:$vec, uimm7:$idx)),
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(SubRegCast (LVSvi v32:$vec, (ULO7 $idx)))>;
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// LVSvr
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def: Pat<(s32 (extractelt v32:$vec, i64:$idx)),
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(SubRegCast (LVSvr v32:$vec, $idx))>;
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// LSVir
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def: Pat<(v32 (insertelt v32:$vec, s32:$val, uimm7:$idx)),
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(LSVir_v (ULO7 $idx), (SuperRegCast $val), $vec)>;
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// LSVrr
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def: Pat<(v32 (insertelt v32:$vec, s32:$val, i64:$idx)),
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(LSVrr_v $idx, (SuperRegCast $val), $vec)>;
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}
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multiclass extract_insert_elem64<ValueType v64, ValueType s64> {
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// LVSvi
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def: Pat<(s64 (extractelt v64:$vec, uimm7:$idx)),
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(LVSvi v64:$vec, (ULO7 $idx))>;
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// LVSvr
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def: Pat<(s64 (extractelt v64:$vec, i64:$idx)),
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(LVSvr v64:$vec, $idx)>;
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// LSVir
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def: Pat<(v64 (insertelt v64:$vec, s64:$val, uimm7:$idx)),
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(LSVir_v (ULO7 $idx), $val, $vec)>;
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// LSVrr
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def: Pat<(v64 (insertelt v64:$vec, s64:$val, i64:$idx)),
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(LSVrr_v $idx, $val, $vec)>;
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}
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multiclass patterns_elem32<ValueType v32, ValueType s32,
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SDPatternOperator ImmOp, SDNodeXForm ImmCast,
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OutPatFrag SubRegCast, OutPatFrag SuperRegCast> {
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defm : vbrd_elem32<v32, s32, ImmOp, ImmCast, SuperRegCast>;
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defm : extract_insert_elem32<v32, s32, SubRegCast, SuperRegCast>;
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}
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multiclass patterns_elem64<ValueType v64, ValueType s64,
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SDPatternOperator ImmOp, SDNodeXForm ImmCast> {
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defm : vbrd_elem64<v64, s64, ImmOp, ImmCast>;
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defm : extract_insert_elem64<v64, s64>;
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}
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defm : patterns_elem32<v256i32, i32, simm7, LO7, l2i, i2l>;
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defm : patterns_elem32<v256f32, f32, simm7fp, LO7FP, l2f, f2l>;
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defm : patterns_elem64<v256i64, i64, simm7, LO7>;
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defm : patterns_elem64<v256f64, f64, simm7fp, LO7FP>;
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