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cb0d7fd331
Main reason is preparation to transform AliasResult to class that contains offset for PartialAlias case. Reviewed By: asbirlea Differential Revision: https://reviews.llvm.org/D98027
735 lines
28 KiB
C++
735 lines
28 KiB
C++
//===- X86AvoidStoreForwardingBlocks.cpp - Avoid HW Store Forward Block ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// If a load follows a store and reloads data that the store has written to
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// memory, Intel microarchitectures can in many cases forward the data directly
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// from the store to the load, This "store forwarding" saves cycles by enabling
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// the load to directly obtain the data instead of accessing the data from
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// cache or memory.
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// A "store forward block" occurs in cases that a store cannot be forwarded to
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// the load. The most typical case of store forward block on Intel Core
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// microarchitecture that a small store cannot be forwarded to a large load.
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// The estimated penalty for a store forward block is ~13 cycles.
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//
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// This pass tries to recognize and handle cases where "store forward block"
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// is created by the compiler when lowering memcpy calls to a sequence
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// of a load and a store.
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//
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// The pass currently only handles cases where memcpy is lowered to
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// XMM/YMM registers, it tries to break the memcpy into smaller copies.
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// breaking the memcpy should be possible since there is no atomicity
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// guarantee for loads and stores to XMM/YMM.
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//
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// It could be better for performance to solve the problem by loading
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// to XMM/YMM then inserting the partial store before storing back from XMM/YMM
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// to memory, but this will result in a more conservative optimization since it
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// requires we prove that all memory accesses between the blocking store and the
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// load must alias/don't alias before we can move the store, whereas the
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// transformation done here is correct regardless to other memory accesses.
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/Function.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/MC/MCInstrDesc.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-avoid-SFB"
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static cl::opt<bool> DisableX86AvoidStoreForwardBlocks(
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"x86-disable-avoid-SFB", cl::Hidden,
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cl::desc("X86: Disable Store Forwarding Blocks fixup."), cl::init(false));
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static cl::opt<unsigned> X86AvoidSFBInspectionLimit(
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"x86-sfb-inspection-limit",
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cl::desc("X86: Number of instructions backward to "
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"inspect for store forwarding blocks."),
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cl::init(20), cl::Hidden);
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namespace {
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using DisplacementSizeMap = std::map<int64_t, unsigned>;
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class X86AvoidSFBPass : public MachineFunctionPass {
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public:
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static char ID;
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X86AvoidSFBPass() : MachineFunctionPass(ID) { }
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StringRef getPassName() const override {
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return "X86 Avoid Store Forwarding Blocks";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<AAResultsWrapperPass>();
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}
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private:
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MachineRegisterInfo *MRI = nullptr;
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const X86InstrInfo *TII = nullptr;
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const X86RegisterInfo *TRI = nullptr;
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SmallVector<std::pair<MachineInstr *, MachineInstr *>, 2>
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BlockedLoadsStoresPairs;
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SmallVector<MachineInstr *, 2> ForRemoval;
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AliasAnalysis *AA = nullptr;
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/// Returns couples of Load then Store to memory which look
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/// like a memcpy.
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void findPotentiallylBlockedCopies(MachineFunction &MF);
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/// Break the memcpy's load and store into smaller copies
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/// such that each memory load that was blocked by a smaller store
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/// would now be copied separately.
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void breakBlockedCopies(MachineInstr *LoadInst, MachineInstr *StoreInst,
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const DisplacementSizeMap &BlockingStoresDispSizeMap);
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/// Break a copy of size Size to smaller copies.
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void buildCopies(int Size, MachineInstr *LoadInst, int64_t LdDispImm,
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MachineInstr *StoreInst, int64_t StDispImm,
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int64_t LMMOffset, int64_t SMMOffset);
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void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
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MachineInstr *StoreInst, unsigned NStoreOpcode,
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int64_t StoreDisp, unsigned Size, int64_t LMMOffset,
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int64_t SMMOffset);
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bool alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2) const;
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unsigned getRegSizeInBytes(MachineInstr *Inst);
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};
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} // end anonymous namespace
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char X86AvoidSFBPass::ID = 0;
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INITIALIZE_PASS_BEGIN(X86AvoidSFBPass, DEBUG_TYPE, "Machine code sinking",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
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INITIALIZE_PASS_END(X86AvoidSFBPass, DEBUG_TYPE, "Machine code sinking", false,
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false)
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FunctionPass *llvm::createX86AvoidStoreForwardingBlocks() {
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return new X86AvoidSFBPass();
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}
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static bool isXMMLoadOpcode(unsigned Opcode) {
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return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm ||
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Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm ||
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Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm ||
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Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm ||
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Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm ||
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Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm ||
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Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm ||
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Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm;
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}
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static bool isYMMLoadOpcode(unsigned Opcode) {
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return Opcode == X86::VMOVUPSYrm || Opcode == X86::VMOVAPSYrm ||
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Opcode == X86::VMOVUPDYrm || Opcode == X86::VMOVAPDYrm ||
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Opcode == X86::VMOVDQUYrm || Opcode == X86::VMOVDQAYrm ||
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Opcode == X86::VMOVUPSZ256rm || Opcode == X86::VMOVAPSZ256rm ||
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Opcode == X86::VMOVUPDZ256rm || Opcode == X86::VMOVAPDZ256rm ||
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Opcode == X86::VMOVDQU64Z256rm || Opcode == X86::VMOVDQA64Z256rm ||
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Opcode == X86::VMOVDQU32Z256rm || Opcode == X86::VMOVDQA32Z256rm;
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}
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static bool isPotentialBlockedMemCpyLd(unsigned Opcode) {
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return isXMMLoadOpcode(Opcode) || isYMMLoadOpcode(Opcode);
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}
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static bool isPotentialBlockedMemCpyPair(unsigned LdOpcode, unsigned StOpcode) {
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switch (LdOpcode) {
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case X86::MOVUPSrm:
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case X86::MOVAPSrm:
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return StOpcode == X86::MOVUPSmr || StOpcode == X86::MOVAPSmr;
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case X86::VMOVUPSrm:
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case X86::VMOVAPSrm:
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return StOpcode == X86::VMOVUPSmr || StOpcode == X86::VMOVAPSmr;
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case X86::VMOVUPDrm:
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case X86::VMOVAPDrm:
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return StOpcode == X86::VMOVUPDmr || StOpcode == X86::VMOVAPDmr;
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case X86::VMOVDQUrm:
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case X86::VMOVDQArm:
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return StOpcode == X86::VMOVDQUmr || StOpcode == X86::VMOVDQAmr;
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case X86::VMOVUPSZ128rm:
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case X86::VMOVAPSZ128rm:
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return StOpcode == X86::VMOVUPSZ128mr || StOpcode == X86::VMOVAPSZ128mr;
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case X86::VMOVUPDZ128rm:
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case X86::VMOVAPDZ128rm:
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return StOpcode == X86::VMOVUPDZ128mr || StOpcode == X86::VMOVAPDZ128mr;
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case X86::VMOVUPSYrm:
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case X86::VMOVAPSYrm:
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return StOpcode == X86::VMOVUPSYmr || StOpcode == X86::VMOVAPSYmr;
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case X86::VMOVUPDYrm:
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case X86::VMOVAPDYrm:
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return StOpcode == X86::VMOVUPDYmr || StOpcode == X86::VMOVAPDYmr;
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case X86::VMOVDQUYrm:
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case X86::VMOVDQAYrm:
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return StOpcode == X86::VMOVDQUYmr || StOpcode == X86::VMOVDQAYmr;
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case X86::VMOVUPSZ256rm:
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case X86::VMOVAPSZ256rm:
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return StOpcode == X86::VMOVUPSZ256mr || StOpcode == X86::VMOVAPSZ256mr;
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case X86::VMOVUPDZ256rm:
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case X86::VMOVAPDZ256rm:
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return StOpcode == X86::VMOVUPDZ256mr || StOpcode == X86::VMOVAPDZ256mr;
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case X86::VMOVDQU64Z128rm:
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case X86::VMOVDQA64Z128rm:
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return StOpcode == X86::VMOVDQU64Z128mr || StOpcode == X86::VMOVDQA64Z128mr;
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case X86::VMOVDQU32Z128rm:
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case X86::VMOVDQA32Z128rm:
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return StOpcode == X86::VMOVDQU32Z128mr || StOpcode == X86::VMOVDQA32Z128mr;
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case X86::VMOVDQU64Z256rm:
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case X86::VMOVDQA64Z256rm:
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return StOpcode == X86::VMOVDQU64Z256mr || StOpcode == X86::VMOVDQA64Z256mr;
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case X86::VMOVDQU32Z256rm:
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case X86::VMOVDQA32Z256rm:
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return StOpcode == X86::VMOVDQU32Z256mr || StOpcode == X86::VMOVDQA32Z256mr;
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default:
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return false;
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}
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}
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static bool isPotentialBlockingStoreInst(unsigned Opcode, unsigned LoadOpcode) {
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bool PBlock = false;
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PBlock |= Opcode == X86::MOV64mr || Opcode == X86::MOV64mi32 ||
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Opcode == X86::MOV32mr || Opcode == X86::MOV32mi ||
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Opcode == X86::MOV16mr || Opcode == X86::MOV16mi ||
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Opcode == X86::MOV8mr || Opcode == X86::MOV8mi;
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if (isYMMLoadOpcode(LoadOpcode))
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PBlock |= Opcode == X86::VMOVUPSmr || Opcode == X86::VMOVAPSmr ||
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Opcode == X86::VMOVUPDmr || Opcode == X86::VMOVAPDmr ||
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Opcode == X86::VMOVDQUmr || Opcode == X86::VMOVDQAmr ||
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Opcode == X86::VMOVUPSZ128mr || Opcode == X86::VMOVAPSZ128mr ||
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Opcode == X86::VMOVUPDZ128mr || Opcode == X86::VMOVAPDZ128mr ||
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Opcode == X86::VMOVDQU64Z128mr ||
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Opcode == X86::VMOVDQA64Z128mr ||
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Opcode == X86::VMOVDQU32Z128mr || Opcode == X86::VMOVDQA32Z128mr;
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return PBlock;
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}
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static const int MOV128SZ = 16;
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static const int MOV64SZ = 8;
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static const int MOV32SZ = 4;
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static const int MOV16SZ = 2;
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static const int MOV8SZ = 1;
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static unsigned getYMMtoXMMLoadOpcode(unsigned LoadOpcode) {
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switch (LoadOpcode) {
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case X86::VMOVUPSYrm:
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case X86::VMOVAPSYrm:
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return X86::VMOVUPSrm;
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case X86::VMOVUPDYrm:
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case X86::VMOVAPDYrm:
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return X86::VMOVUPDrm;
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case X86::VMOVDQUYrm:
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case X86::VMOVDQAYrm:
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return X86::VMOVDQUrm;
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case X86::VMOVUPSZ256rm:
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case X86::VMOVAPSZ256rm:
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return X86::VMOVUPSZ128rm;
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case X86::VMOVUPDZ256rm:
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case X86::VMOVAPDZ256rm:
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return X86::VMOVUPDZ128rm;
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case X86::VMOVDQU64Z256rm:
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case X86::VMOVDQA64Z256rm:
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return X86::VMOVDQU64Z128rm;
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case X86::VMOVDQU32Z256rm:
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case X86::VMOVDQA32Z256rm:
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return X86::VMOVDQU32Z128rm;
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default:
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llvm_unreachable("Unexpected Load Instruction Opcode");
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}
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return 0;
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}
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static unsigned getYMMtoXMMStoreOpcode(unsigned StoreOpcode) {
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switch (StoreOpcode) {
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case X86::VMOVUPSYmr:
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case X86::VMOVAPSYmr:
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return X86::VMOVUPSmr;
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case X86::VMOVUPDYmr:
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case X86::VMOVAPDYmr:
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return X86::VMOVUPDmr;
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case X86::VMOVDQUYmr:
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case X86::VMOVDQAYmr:
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return X86::VMOVDQUmr;
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case X86::VMOVUPSZ256mr:
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case X86::VMOVAPSZ256mr:
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return X86::VMOVUPSZ128mr;
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case X86::VMOVUPDZ256mr:
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case X86::VMOVAPDZ256mr:
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return X86::VMOVUPDZ128mr;
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case X86::VMOVDQU64Z256mr:
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case X86::VMOVDQA64Z256mr:
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return X86::VMOVDQU64Z128mr;
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case X86::VMOVDQU32Z256mr:
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case X86::VMOVDQA32Z256mr:
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return X86::VMOVDQU32Z128mr;
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default:
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llvm_unreachable("Unexpected Load Instruction Opcode");
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}
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return 0;
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}
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static int getAddrOffset(const MachineInstr *MI) {
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const MCInstrDesc &Descl = MI->getDesc();
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int AddrOffset = X86II::getMemoryOperandNo(Descl.TSFlags);
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assert(AddrOffset != -1 && "Expected Memory Operand");
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AddrOffset += X86II::getOperandBias(Descl);
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return AddrOffset;
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}
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static MachineOperand &getBaseOperand(MachineInstr *MI) {
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int AddrOffset = getAddrOffset(MI);
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return MI->getOperand(AddrOffset + X86::AddrBaseReg);
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}
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static MachineOperand &getDispOperand(MachineInstr *MI) {
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int AddrOffset = getAddrOffset(MI);
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return MI->getOperand(AddrOffset + X86::AddrDisp);
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}
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// Relevant addressing modes contain only base register and immediate
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// displacement or frameindex and immediate displacement.
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// TODO: Consider expanding to other addressing modes in the future
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static bool isRelevantAddressingMode(MachineInstr *MI) {
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int AddrOffset = getAddrOffset(MI);
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const MachineOperand &Base = getBaseOperand(MI);
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const MachineOperand &Disp = getDispOperand(MI);
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const MachineOperand &Scale = MI->getOperand(AddrOffset + X86::AddrScaleAmt);
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const MachineOperand &Index = MI->getOperand(AddrOffset + X86::AddrIndexReg);
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const MachineOperand &Segment = MI->getOperand(AddrOffset + X86::AddrSegmentReg);
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if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI()))
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return false;
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if (!Disp.isImm())
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return false;
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if (Scale.getImm() != 1)
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return false;
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if (!(Index.isReg() && Index.getReg() == X86::NoRegister))
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return false;
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if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister))
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return false;
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return true;
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}
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// Collect potentially blocking stores.
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// Limit the number of instructions backwards we want to inspect
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// since the effect of store block won't be visible if the store
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// and load instructions have enough instructions in between to
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// keep the core busy.
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static SmallVector<MachineInstr *, 2>
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findPotentialBlockers(MachineInstr *LoadInst) {
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SmallVector<MachineInstr *, 2> PotentialBlockers;
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unsigned BlockCount = 0;
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const unsigned InspectionLimit = X86AvoidSFBInspectionLimit;
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for (auto PBInst = std::next(MachineBasicBlock::reverse_iterator(LoadInst)),
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E = LoadInst->getParent()->rend();
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PBInst != E; ++PBInst) {
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if (PBInst->isMetaInstruction())
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continue;
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BlockCount++;
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if (BlockCount >= InspectionLimit)
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break;
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MachineInstr &MI = *PBInst;
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if (MI.getDesc().isCall())
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return PotentialBlockers;
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PotentialBlockers.push_back(&MI);
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}
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// If we didn't get to the instructions limit try predecessing blocks.
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// Ideally we should traverse the predecessor blocks in depth with some
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// coloring algorithm, but for now let's just look at the first order
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// predecessors.
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if (BlockCount < InspectionLimit) {
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MachineBasicBlock *MBB = LoadInst->getParent();
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int LimitLeft = InspectionLimit - BlockCount;
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for (MachineBasicBlock::pred_iterator PB = MBB->pred_begin(),
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PE = MBB->pred_end();
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PB != PE; ++PB) {
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MachineBasicBlock *PMBB = *PB;
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int PredCount = 0;
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for (MachineBasicBlock::reverse_iterator PBInst = PMBB->rbegin(),
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PME = PMBB->rend();
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PBInst != PME; ++PBInst) {
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if (PBInst->isMetaInstruction())
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continue;
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PredCount++;
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if (PredCount >= LimitLeft)
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break;
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if (PBInst->getDesc().isCall())
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break;
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PotentialBlockers.push_back(&*PBInst);
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}
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}
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}
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return PotentialBlockers;
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}
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void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode,
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int64_t LoadDisp, MachineInstr *StoreInst,
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unsigned NStoreOpcode, int64_t StoreDisp,
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unsigned Size, int64_t LMMOffset,
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int64_t SMMOffset) {
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MachineOperand &LoadBase = getBaseOperand(LoadInst);
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MachineOperand &StoreBase = getBaseOperand(StoreInst);
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MachineBasicBlock *MBB = LoadInst->getParent();
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MachineMemOperand *LMMO = *LoadInst->memoperands_begin();
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MachineMemOperand *SMMO = *StoreInst->memoperands_begin();
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Register Reg1 = MRI->createVirtualRegister(
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TII->getRegClass(TII->get(NLoadOpcode), 0, TRI, *(MBB->getParent())));
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MachineInstr *NewLoad =
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BuildMI(*MBB, LoadInst, LoadInst->getDebugLoc(), TII->get(NLoadOpcode),
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Reg1)
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.add(LoadBase)
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.addImm(1)
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.addReg(X86::NoRegister)
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.addImm(LoadDisp)
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.addReg(X86::NoRegister)
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.addMemOperand(
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MBB->getParent()->getMachineMemOperand(LMMO, LMMOffset, Size));
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if (LoadBase.isReg())
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getBaseOperand(NewLoad).setIsKill(false);
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LLVM_DEBUG(NewLoad->dump());
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// If the load and store are consecutive, use the loadInst location to
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// reduce register pressure.
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MachineInstr *StInst = StoreInst;
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auto PrevInstrIt = prev_nodbg(MachineBasicBlock::instr_iterator(StoreInst),
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MBB->instr_begin());
|
|
if (PrevInstrIt.getNodePtr() == LoadInst)
|
|
StInst = LoadInst;
|
|
MachineInstr *NewStore =
|
|
BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode))
|
|
.add(StoreBase)
|
|
.addImm(1)
|
|
.addReg(X86::NoRegister)
|
|
.addImm(StoreDisp)
|
|
.addReg(X86::NoRegister)
|
|
.addReg(Reg1)
|
|
.addMemOperand(
|
|
MBB->getParent()->getMachineMemOperand(SMMO, SMMOffset, Size));
|
|
if (StoreBase.isReg())
|
|
getBaseOperand(NewStore).setIsKill(false);
|
|
MachineOperand &StoreSrcVReg = StoreInst->getOperand(X86::AddrNumOperands);
|
|
assert(StoreSrcVReg.isReg() && "Expected virtual register");
|
|
NewStore->getOperand(X86::AddrNumOperands).setIsKill(StoreSrcVReg.isKill());
|
|
LLVM_DEBUG(NewStore->dump());
|
|
}
|
|
|
|
void X86AvoidSFBPass::buildCopies(int Size, MachineInstr *LoadInst,
|
|
int64_t LdDispImm, MachineInstr *StoreInst,
|
|
int64_t StDispImm, int64_t LMMOffset,
|
|
int64_t SMMOffset) {
|
|
int LdDisp = LdDispImm;
|
|
int StDisp = StDispImm;
|
|
while (Size > 0) {
|
|
if ((Size - MOV128SZ >= 0) && isYMMLoadOpcode(LoadInst->getOpcode())) {
|
|
Size = Size - MOV128SZ;
|
|
buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp,
|
|
StoreInst, getYMMtoXMMStoreOpcode(StoreInst->getOpcode()),
|
|
StDisp, MOV128SZ, LMMOffset, SMMOffset);
|
|
LdDisp += MOV128SZ;
|
|
StDisp += MOV128SZ;
|
|
LMMOffset += MOV128SZ;
|
|
SMMOffset += MOV128SZ;
|
|
continue;
|
|
}
|
|
if (Size - MOV64SZ >= 0) {
|
|
Size = Size - MOV64SZ;
|
|
buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp,
|
|
MOV64SZ, LMMOffset, SMMOffset);
|
|
LdDisp += MOV64SZ;
|
|
StDisp += MOV64SZ;
|
|
LMMOffset += MOV64SZ;
|
|
SMMOffset += MOV64SZ;
|
|
continue;
|
|
}
|
|
if (Size - MOV32SZ >= 0) {
|
|
Size = Size - MOV32SZ;
|
|
buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp,
|
|
MOV32SZ, LMMOffset, SMMOffset);
|
|
LdDisp += MOV32SZ;
|
|
StDisp += MOV32SZ;
|
|
LMMOffset += MOV32SZ;
|
|
SMMOffset += MOV32SZ;
|
|
continue;
|
|
}
|
|
if (Size - MOV16SZ >= 0) {
|
|
Size = Size - MOV16SZ;
|
|
buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp,
|
|
MOV16SZ, LMMOffset, SMMOffset);
|
|
LdDisp += MOV16SZ;
|
|
StDisp += MOV16SZ;
|
|
LMMOffset += MOV16SZ;
|
|
SMMOffset += MOV16SZ;
|
|
continue;
|
|
}
|
|
if (Size - MOV8SZ >= 0) {
|
|
Size = Size - MOV8SZ;
|
|
buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp,
|
|
MOV8SZ, LMMOffset, SMMOffset);
|
|
LdDisp += MOV8SZ;
|
|
StDisp += MOV8SZ;
|
|
LMMOffset += MOV8SZ;
|
|
SMMOffset += MOV8SZ;
|
|
continue;
|
|
}
|
|
}
|
|
assert(Size == 0 && "Wrong size division");
|
|
}
|
|
|
|
static void updateKillStatus(MachineInstr *LoadInst, MachineInstr *StoreInst) {
|
|
MachineOperand &LoadBase = getBaseOperand(LoadInst);
|
|
MachineOperand &StoreBase = getBaseOperand(StoreInst);
|
|
auto *StorePrevNonDbgInstr =
|
|
prev_nodbg(MachineBasicBlock::instr_iterator(StoreInst),
|
|
LoadInst->getParent()->instr_begin())
|
|
.getNodePtr();
|
|
if (LoadBase.isReg()) {
|
|
MachineInstr *LastLoad = LoadInst->getPrevNode();
|
|
// If the original load and store to xmm/ymm were consecutive
|
|
// then the partial copies were also created in
|
|
// a consecutive order to reduce register pressure,
|
|
// and the location of the last load is before the last store.
|
|
if (StorePrevNonDbgInstr == LoadInst)
|
|
LastLoad = LoadInst->getPrevNode()->getPrevNode();
|
|
getBaseOperand(LastLoad).setIsKill(LoadBase.isKill());
|
|
}
|
|
if (StoreBase.isReg()) {
|
|
MachineInstr *StInst = StoreInst;
|
|
if (StorePrevNonDbgInstr == LoadInst)
|
|
StInst = LoadInst;
|
|
getBaseOperand(StInst->getPrevNode()).setIsKill(StoreBase.isKill());
|
|
}
|
|
}
|
|
|
|
bool X86AvoidSFBPass::alias(const MachineMemOperand &Op1,
|
|
const MachineMemOperand &Op2) const {
|
|
if (!Op1.getValue() || !Op2.getValue())
|
|
return true;
|
|
|
|
int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset());
|
|
int64_t Overlapa = Op1.getSize() + Op1.getOffset() - MinOffset;
|
|
int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset;
|
|
|
|
return !AA->isNoAlias(
|
|
MemoryLocation(Op1.getValue(), Overlapa, Op1.getAAInfo()),
|
|
MemoryLocation(Op2.getValue(), Overlapb, Op2.getAAInfo()));
|
|
}
|
|
|
|
void X86AvoidSFBPass::findPotentiallylBlockedCopies(MachineFunction &MF) {
|
|
for (auto &MBB : MF)
|
|
for (auto &MI : MBB) {
|
|
if (!isPotentialBlockedMemCpyLd(MI.getOpcode()))
|
|
continue;
|
|
int DefVR = MI.getOperand(0).getReg();
|
|
if (!MRI->hasOneNonDBGUse(DefVR))
|
|
continue;
|
|
for (auto UI = MRI->use_nodbg_begin(DefVR), UE = MRI->use_nodbg_end();
|
|
UI != UE;) {
|
|
MachineOperand &StoreMO = *UI++;
|
|
MachineInstr &StoreMI = *StoreMO.getParent();
|
|
// Skip cases where the memcpy may overlap.
|
|
if (StoreMI.getParent() == MI.getParent() &&
|
|
isPotentialBlockedMemCpyPair(MI.getOpcode(), StoreMI.getOpcode()) &&
|
|
isRelevantAddressingMode(&MI) &&
|
|
isRelevantAddressingMode(&StoreMI) &&
|
|
MI.hasOneMemOperand() && StoreMI.hasOneMemOperand()) {
|
|
if (!alias(**MI.memoperands_begin(), **StoreMI.memoperands_begin()))
|
|
BlockedLoadsStoresPairs.push_back(std::make_pair(&MI, &StoreMI));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned X86AvoidSFBPass::getRegSizeInBytes(MachineInstr *LoadInst) {
|
|
const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI,
|
|
*LoadInst->getParent()->getParent());
|
|
return TRI->getRegSizeInBits(*TRC) / 8;
|
|
}
|
|
|
|
void X86AvoidSFBPass::breakBlockedCopies(
|
|
MachineInstr *LoadInst, MachineInstr *StoreInst,
|
|
const DisplacementSizeMap &BlockingStoresDispSizeMap) {
|
|
int64_t LdDispImm = getDispOperand(LoadInst).getImm();
|
|
int64_t StDispImm = getDispOperand(StoreInst).getImm();
|
|
int64_t LMMOffset = 0;
|
|
int64_t SMMOffset = 0;
|
|
|
|
int64_t LdDisp1 = LdDispImm;
|
|
int64_t LdDisp2 = 0;
|
|
int64_t StDisp1 = StDispImm;
|
|
int64_t StDisp2 = 0;
|
|
unsigned Size1 = 0;
|
|
unsigned Size2 = 0;
|
|
int64_t LdStDelta = StDispImm - LdDispImm;
|
|
|
|
for (auto DispSizePair : BlockingStoresDispSizeMap) {
|
|
LdDisp2 = DispSizePair.first;
|
|
StDisp2 = DispSizePair.first + LdStDelta;
|
|
Size2 = DispSizePair.second;
|
|
// Avoid copying overlapping areas.
|
|
if (LdDisp2 < LdDisp1) {
|
|
int OverlapDelta = LdDisp1 - LdDisp2;
|
|
LdDisp2 += OverlapDelta;
|
|
StDisp2 += OverlapDelta;
|
|
Size2 -= OverlapDelta;
|
|
}
|
|
Size1 = LdDisp2 - LdDisp1;
|
|
|
|
// Build a copy for the point until the current blocking store's
|
|
// displacement.
|
|
buildCopies(Size1, LoadInst, LdDisp1, StoreInst, StDisp1, LMMOffset,
|
|
SMMOffset);
|
|
// Build a copy for the current blocking store.
|
|
buildCopies(Size2, LoadInst, LdDisp2, StoreInst, StDisp2, LMMOffset + Size1,
|
|
SMMOffset + Size1);
|
|
LdDisp1 = LdDisp2 + Size2;
|
|
StDisp1 = StDisp2 + Size2;
|
|
LMMOffset += Size1 + Size2;
|
|
SMMOffset += Size1 + Size2;
|
|
}
|
|
unsigned Size3 = (LdDispImm + getRegSizeInBytes(LoadInst)) - LdDisp1;
|
|
buildCopies(Size3, LoadInst, LdDisp1, StoreInst, StDisp1, LMMOffset,
|
|
LMMOffset);
|
|
}
|
|
|
|
static bool hasSameBaseOpValue(MachineInstr *LoadInst,
|
|
MachineInstr *StoreInst) {
|
|
const MachineOperand &LoadBase = getBaseOperand(LoadInst);
|
|
const MachineOperand &StoreBase = getBaseOperand(StoreInst);
|
|
if (LoadBase.isReg() != StoreBase.isReg())
|
|
return false;
|
|
if (LoadBase.isReg())
|
|
return LoadBase.getReg() == StoreBase.getReg();
|
|
return LoadBase.getIndex() == StoreBase.getIndex();
|
|
}
|
|
|
|
static bool isBlockingStore(int64_t LoadDispImm, unsigned LoadSize,
|
|
int64_t StoreDispImm, unsigned StoreSize) {
|
|
return ((StoreDispImm >= LoadDispImm) &&
|
|
(StoreDispImm <= LoadDispImm + (LoadSize - StoreSize)));
|
|
}
|
|
|
|
// Keep track of all stores blocking a load
|
|
static void
|
|
updateBlockingStoresDispSizeMap(DisplacementSizeMap &BlockingStoresDispSizeMap,
|
|
int64_t DispImm, unsigned Size) {
|
|
if (BlockingStoresDispSizeMap.count(DispImm)) {
|
|
// Choose the smallest blocking store starting at this displacement.
|
|
if (BlockingStoresDispSizeMap[DispImm] > Size)
|
|
BlockingStoresDispSizeMap[DispImm] = Size;
|
|
|
|
} else
|
|
BlockingStoresDispSizeMap[DispImm] = Size;
|
|
}
|
|
|
|
// Remove blocking stores contained in each other.
|
|
static void
|
|
removeRedundantBlockingStores(DisplacementSizeMap &BlockingStoresDispSizeMap) {
|
|
if (BlockingStoresDispSizeMap.size() <= 1)
|
|
return;
|
|
|
|
SmallVector<std::pair<int64_t, unsigned>, 0> DispSizeStack;
|
|
for (auto DispSizePair : BlockingStoresDispSizeMap) {
|
|
int64_t CurrDisp = DispSizePair.first;
|
|
unsigned CurrSize = DispSizePair.second;
|
|
while (DispSizeStack.size()) {
|
|
int64_t PrevDisp = DispSizeStack.back().first;
|
|
unsigned PrevSize = DispSizeStack.back().second;
|
|
if (CurrDisp + CurrSize > PrevDisp + PrevSize)
|
|
break;
|
|
DispSizeStack.pop_back();
|
|
}
|
|
DispSizeStack.push_back(DispSizePair);
|
|
}
|
|
BlockingStoresDispSizeMap.clear();
|
|
for (auto Disp : DispSizeStack)
|
|
BlockingStoresDispSizeMap.insert(Disp);
|
|
}
|
|
|
|
bool X86AvoidSFBPass::runOnMachineFunction(MachineFunction &MF) {
|
|
bool Changed = false;
|
|
|
|
if (DisableX86AvoidStoreForwardBlocks || skipFunction(MF.getFunction()) ||
|
|
!MF.getSubtarget<X86Subtarget>().is64Bit())
|
|
return false;
|
|
|
|
MRI = &MF.getRegInfo();
|
|
assert(MRI->isSSA() && "Expected MIR to be in SSA form");
|
|
TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
|
|
TRI = MF.getSubtarget<X86Subtarget>().getRegisterInfo();
|
|
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
|
|
LLVM_DEBUG(dbgs() << "Start X86AvoidStoreForwardBlocks\n";);
|
|
// Look for a load then a store to XMM/YMM which look like a memcpy
|
|
findPotentiallylBlockedCopies(MF);
|
|
|
|
for (auto LoadStoreInstPair : BlockedLoadsStoresPairs) {
|
|
MachineInstr *LoadInst = LoadStoreInstPair.first;
|
|
int64_t LdDispImm = getDispOperand(LoadInst).getImm();
|
|
DisplacementSizeMap BlockingStoresDispSizeMap;
|
|
|
|
SmallVector<MachineInstr *, 2> PotentialBlockers =
|
|
findPotentialBlockers(LoadInst);
|
|
for (auto *PBInst : PotentialBlockers) {
|
|
if (!isPotentialBlockingStoreInst(PBInst->getOpcode(),
|
|
LoadInst->getOpcode()) ||
|
|
!isRelevantAddressingMode(PBInst) || !PBInst->hasOneMemOperand())
|
|
continue;
|
|
int64_t PBstDispImm = getDispOperand(PBInst).getImm();
|
|
unsigned PBstSize = (*PBInst->memoperands_begin())->getSize();
|
|
// This check doesn't cover all cases, but it will suffice for now.
|
|
// TODO: take branch probability into consideration, if the blocking
|
|
// store is in an unreached block, breaking the memcopy could lose
|
|
// performance.
|
|
if (hasSameBaseOpValue(LoadInst, PBInst) &&
|
|
isBlockingStore(LdDispImm, getRegSizeInBytes(LoadInst), PBstDispImm,
|
|
PBstSize))
|
|
updateBlockingStoresDispSizeMap(BlockingStoresDispSizeMap, PBstDispImm,
|
|
PBstSize);
|
|
}
|
|
|
|
if (BlockingStoresDispSizeMap.empty())
|
|
continue;
|
|
|
|
// We found a store forward block, break the memcpy's load and store
|
|
// into smaller copies such that each smaller store that was causing
|
|
// a store block would now be copied separately.
|
|
MachineInstr *StoreInst = LoadStoreInstPair.second;
|
|
LLVM_DEBUG(dbgs() << "Blocked load and store instructions: \n");
|
|
LLVM_DEBUG(LoadInst->dump());
|
|
LLVM_DEBUG(StoreInst->dump());
|
|
LLVM_DEBUG(dbgs() << "Replaced with:\n");
|
|
removeRedundantBlockingStores(BlockingStoresDispSizeMap);
|
|
breakBlockedCopies(LoadInst, StoreInst, BlockingStoresDispSizeMap);
|
|
updateKillStatus(LoadInst, StoreInst);
|
|
ForRemoval.push_back(LoadInst);
|
|
ForRemoval.push_back(StoreInst);
|
|
}
|
|
for (auto *RemovedInst : ForRemoval) {
|
|
RemovedInst->eraseFromParent();
|
|
}
|
|
ForRemoval.clear();
|
|
BlockedLoadsStoresPairs.clear();
|
|
LLVM_DEBUG(dbgs() << "End X86AvoidStoreForwardBlocks\n";);
|
|
|
|
return Changed;
|
|
}
|