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b7262b7cbf
-Deprecate -mmpx and -mno-mpx command line options -Remove CPUID detection of mpx for -march=native -Remove MPX from all CPUs -Remove MPX preprocessor define I've left the "mpx" string in the backend so we don't fail on old IR, but its not connected to anything. gcc has also deprecated these command line options. https://www.phoronix.com/scan.php?page=news_item&px=GCC-Patch-To-Drop-MPX Differential Revision: https://reviews.llvm.org/D66669 llvm-svn: 370393
78 lines
3.6 KiB
TableGen
78 lines
3.6 KiB
TableGen
//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 MPX instruction set, defining the
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// instructions, and properties of the instructions which are needed for code
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// generation, machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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// FIXME: Investigate a better scheduler class if MPX is ever used inside LLVM.
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let SchedRW = [WriteSystem] in {
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multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
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def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
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OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
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Requires<[Not64BitMode]>;
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def 64rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
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OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
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Requires<[In64BitMode]>;
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}
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defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
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multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
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def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[Not64BitMode]>;
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def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[In64BitMode]>;
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def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[Not64BitMode]>;
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def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[In64BitMode]>;
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}
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defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable;
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defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable;
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defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable;
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def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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NotMemoryFoldable;
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let mayLoad = 1 in {
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def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[Not64BitMode]>, NotMemoryFoldable;
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def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[In64BitMode]>, NotMemoryFoldable;
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}
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let isCodeGenOnly = 1, ForceDisassemble = 1 in
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def BNDMOVrr_REV : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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NotMemoryFoldable;
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let mayStore = 1 in {
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def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[Not64BitMode]>, NotMemoryFoldable;
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def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[In64BitMode]>, NotMemoryFoldable;
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def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src),
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"bndstx\t{$src, $dst|$dst, $src}", []>, PS;
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}
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let mayLoad = 1 in
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def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
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"bndldx\t{$src, $dst|$dst, $src}", []>, PS;
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} // SchedRW
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