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df7a8b162e
This makes it possible for targets to define their own MCObjectFileInfo. This MCObjectFileInfo is then used to determine things like section alignment. This is a follow up to D101462 and prepares for the RISCV backend defining the text section alignment depending on the enabled extensions. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D101921
393 lines
14 KiB
C++
393 lines
14 KiB
C++
//===- MachineInstrTest.cpp -----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/ModuleSlotTracker.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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namespace {
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// Include helper functions to ease the manipulation of MachineFunctions.
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#include "MFCommon.inc"
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std::unique_ptr<MCContext> createMCContext(MCAsmInfo *AsmInfo) {
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Triple TheTriple(/*ArchStr=*/"", /*VendorStr=*/"", /*OSStr=*/"",
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/*EnvironmentStr=*/"elf");
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return std::make_unique<MCContext>(TheTriple, AsmInfo, nullptr, nullptr,
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nullptr, nullptr, false);
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}
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// This test makes sure that MachineInstr::isIdenticalTo handles Defs correctly
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// for various combinations of IgnoreDefs, and also that it is symmetrical.
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TEST(IsIdenticalToTest, DifferentDefs) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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unsigned short NumOps = 2;
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unsigned char NumDefs = 1;
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MCOperandInfo OpInfo[] = {
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{0, 0, MCOI::OPERAND_REGISTER, 0},
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{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
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MCInstrDesc MCID = {
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0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef,
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0, nullptr, nullptr, OpInfo};
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// Create two MIs with different virtual reg defs and the same uses.
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unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
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unsigned VirtualDef2 = -43;
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unsigned VirtualUse = -44;
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auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
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MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
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auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc());
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MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
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// Check that they are identical when we ignore virtual register defs, but not
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// when we check defs.
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ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs));
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ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs));
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ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs));
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ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs));
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// Create two MIs with different virtual reg defs, and a def or use of a
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// sentinel register.
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unsigned SentinelReg = 0;
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auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc());
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MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
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auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc());
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MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
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// Check that they are never identical.
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ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs));
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ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs));
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ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs));
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ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs));
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}
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// Check that MachineInstrExpressionTrait::isEqual is symmetric and in sync with
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// MachineInstrExpressionTrait::getHashValue
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void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) {
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bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2);
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bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1);
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ASSERT_EQ(IsEqual1, IsEqual2);
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auto Hash1 = MachineInstrExpressionTrait::getHashValue(MI1);
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auto Hash2 = MachineInstrExpressionTrait::getHashValue(MI2);
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ASSERT_EQ(IsEqual1, Hash1 == Hash2);
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}
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// This test makes sure that MachineInstrExpressionTraits::isEqual is in sync
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// with MachineInstrExpressionTraits::getHashValue.
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TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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unsigned short NumOps = 2;
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unsigned char NumDefs = 1;
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MCOperandInfo OpInfo[] = {
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{0, 0, MCOI::OPERAND_REGISTER, 0},
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{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
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MCInstrDesc MCID = {
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0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef,
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0, nullptr, nullptr, OpInfo};
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// Define a series of instructions with different kinds of operands and make
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// sure that the hash function is consistent with isEqual for various
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// combinations of them.
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unsigned VirtualDef1 = -42;
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unsigned VirtualDef2 = -43;
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unsigned VirtualReg = -44;
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unsigned SentinelReg = 0;
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unsigned PhysicalReg = 45;
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auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc());
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VD1VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
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auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc());
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VD2VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
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auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc());
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VD1SU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1SU->addOperand(*MF,
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MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
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auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc());
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VD1SD->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1SD->addOperand(*MF,
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MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
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auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc());
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VD2PU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2PU->addOperand(*MF,
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MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
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auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc());
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VD2PD->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2PD->addOperand(*MF,
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MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true));
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checkHashAndIsEqualMatch(VD1VU, VD2VU);
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checkHashAndIsEqualMatch(VD1VU, VD1SU);
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checkHashAndIsEqualMatch(VD1VU, VD1SD);
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checkHashAndIsEqualMatch(VD1VU, VD2PU);
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checkHashAndIsEqualMatch(VD1VU, VD2PD);
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checkHashAndIsEqualMatch(VD2VU, VD1SU);
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checkHashAndIsEqualMatch(VD2VU, VD1SD);
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checkHashAndIsEqualMatch(VD2VU, VD2PU);
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checkHashAndIsEqualMatch(VD2VU, VD2PD);
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checkHashAndIsEqualMatch(VD1SU, VD1SD);
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checkHashAndIsEqualMatch(VD1SU, VD2PU);
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checkHashAndIsEqualMatch(VD1SU, VD2PD);
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checkHashAndIsEqualMatch(VD1SD, VD2PU);
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checkHashAndIsEqualMatch(VD1SD, VD2PD);
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checkHashAndIsEqualMatch(VD2PU, VD2PD);
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}
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TEST(MachineInstrPrintingTest, DebugLocPrinting) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0};
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MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 0, nullptr, nullptr, &OpInfo};
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DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
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DISubprogram *DIS = DISubprogram::getDistinct(
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Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero,
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DISubprogram::SPFlagZero, nullptr);
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DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
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DebugLoc DL(DIL);
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MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);
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MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));
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std::string str;
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raw_string_ostream OS(str);
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MI->print(OS, /*IsStandalone*/true, /*SkipOpers*/false, /*SkipDebugLoc*/false,
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/*AddNewLine*/false);
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ASSERT_TRUE(
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StringRef(OS.str()).startswith("$noreg = UNKNOWN debug-location "));
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ASSERT_TRUE(
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StringRef(OS.str()).endswith("filename:1:5"));
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}
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TEST(MachineInstrSpan, DistanceBegin) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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auto MBB = MF->CreateMachineBasicBlock();
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
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auto MII = MBB->begin();
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MachineInstrSpan MIS(MII, MBB);
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ASSERT_TRUE(MIS.empty());
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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MBB->insert(MII, MI);
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ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
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}
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TEST(MachineInstrSpan, DistanceEnd) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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auto MBB = MF->CreateMachineBasicBlock();
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
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auto MII = MBB->end();
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MachineInstrSpan MIS(MII, MBB);
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ASSERT_TRUE(MIS.empty());
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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MBB->insert(MII, MI);
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ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
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}
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TEST(MachineInstrExtraInfo, AddExtraInfo) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MAI = MCAsmInfo();
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auto MC = createMCContext(&MAI);
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auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
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MachineMemOperand::MOLoad, 8, Align(8));
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SmallVector<MachineMemOperand *, 2> MMOs;
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MMOs.push_back(MMO);
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MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
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MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
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MDNode *MDN = MDNode::getDistinct(Ctx, None);
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ASSERT_TRUE(MI->memoperands_empty());
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ASSERT_FALSE(MI->getPreInstrSymbol());
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ASSERT_FALSE(MI->getPostInstrSymbol());
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ASSERT_FALSE(MI->getHeapAllocMarker());
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MI->setMemRefs(*MF, MMOs);
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ASSERT_TRUE(MI->memoperands().size() == 1);
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ASSERT_FALSE(MI->getPreInstrSymbol());
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ASSERT_FALSE(MI->getPostInstrSymbol());
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ASSERT_FALSE(MI->getHeapAllocMarker());
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MI->setPreInstrSymbol(*MF, Sym1);
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ASSERT_TRUE(MI->memoperands().size() == 1);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_FALSE(MI->getPostInstrSymbol());
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ASSERT_FALSE(MI->getHeapAllocMarker());
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MI->setPostInstrSymbol(*MF, Sym2);
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ASSERT_TRUE(MI->memoperands().size() == 1);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
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ASSERT_FALSE(MI->getHeapAllocMarker());
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MI->setHeapAllocMarker(*MF, MDN);
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ASSERT_TRUE(MI->memoperands().size() == 1);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
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ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
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}
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TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MAI = MCAsmInfo();
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auto MC = createMCContext(&MAI);
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auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
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MachineMemOperand::MOLoad, 8, Align(8));
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SmallVector<MachineMemOperand *, 2> MMOs;
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MMOs.push_back(MMO);
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MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
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MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
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MDNode *MDN = MDNode::getDistinct(Ctx, None);
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MI->setMemRefs(*MF, MMOs);
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MI->setPreInstrSymbol(*MF, Sym1);
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MI->setPostInstrSymbol(*MF, Sym2);
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MI->setHeapAllocMarker(*MF, MDN);
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MMOs.push_back(MMO);
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MI->setMemRefs(*MF, MMOs);
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ASSERT_TRUE(MI->memoperands().size() == 2);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
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ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
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MI->setPostInstrSymbol(*MF, Sym1);
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ASSERT_TRUE(MI->memoperands().size() == 2);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getPostInstrSymbol() == Sym1);
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ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
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}
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TEST(MachineInstrExtraInfo, RemoveExtraInfo) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MAI = MCAsmInfo();
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auto MC = createMCContext(&MAI);
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auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
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MachineMemOperand::MOLoad, 8, Align(8));
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SmallVector<MachineMemOperand *, 2> MMOs;
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MMOs.push_back(MMO);
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MMOs.push_back(MMO);
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MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
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MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
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MDNode *MDN = MDNode::getDistinct(Ctx, None);
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MI->setMemRefs(*MF, MMOs);
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MI->setPreInstrSymbol(*MF, Sym1);
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MI->setPostInstrSymbol(*MF, Sym2);
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MI->setHeapAllocMarker(*MF, MDN);
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MI->setPostInstrSymbol(*MF, nullptr);
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ASSERT_TRUE(MI->memoperands().size() == 2);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_FALSE(MI->getPostInstrSymbol());
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ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
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MI->setHeapAllocMarker(*MF, nullptr);
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ASSERT_TRUE(MI->memoperands().size() == 2);
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ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
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ASSERT_FALSE(MI->getPostInstrSymbol());
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ASSERT_FALSE(MI->getHeapAllocMarker());
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MI->setPreInstrSymbol(*MF, nullptr);
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ASSERT_TRUE(MI->memoperands().size() == 2);
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ASSERT_FALSE(MI->getPreInstrSymbol());
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ASSERT_FALSE(MI->getPostInstrSymbol());
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ASSERT_FALSE(MI->getHeapAllocMarker());
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MI->setMemRefs(*MF, {});
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ASSERT_TRUE(MI->memoperands_empty());
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ASSERT_FALSE(MI->getPreInstrSymbol());
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ASSERT_FALSE(MI->getPostInstrSymbol());
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ASSERT_FALSE(MI->getHeapAllocMarker());
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}
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static_assert(std::is_trivially_copyable<MCOperand>::value,
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"trivially copyable");
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} // end namespace
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