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ad0b9a0feb
This refactors option -disable-mve-tail-predication to take different arguments so that we have 1 option to control tail-predication rather than several different ones. This is also a prep step for D82953, in which we want to reject reductions unless that is requested with this option. Differential Revision: https://reviews.llvm.org/D83133
281 lines
10 KiB
C++
281 lines
10 KiB
C++
//===- ARMTargetTransformInfo.h - ARM specific TTI --------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// ARM target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
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#include "ARM.h"
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#include "ARMSubtarget.h"
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#include "ARMTargetMachine.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Constant.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/SubtargetFeature.h"
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namespace llvm {
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class APInt;
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class ARMTargetLowering;
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class Instruction;
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class Loop;
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class SCEV;
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class ScalarEvolution;
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class Type;
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class Value;
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namespace TailPredication {
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enum Mode {
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Disabled = 0,
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EnabledNoReductions,
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Enabled,
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ForceEnabledNoReductions,
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ForceEnabled
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};
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}
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class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
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using BaseT = BasicTTIImplBase<ARMTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const ARMSubtarget *ST;
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const ARMTargetLowering *TLI;
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// Currently the following features are excluded from InlineFeaturesAllowed.
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// ModeThumb, FeatureNoARM, ModeSoftFloat, FeatureFP64, FeatureD32
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// Depending on whether they are set or unset, different
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// instructions/registers are available. For example, inlining a callee with
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// -thumb-mode in a caller with +thumb-mode, may cause the assembler to
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// fail if the callee uses ARM only instructions, e.g. in inline asm.
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const FeatureBitset InlineFeaturesAllowed = {
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ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
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ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
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ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
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ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
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ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
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ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
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ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
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ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
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ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
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ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
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ARM::FeaturePrefISHSTBarrier, ARM::FeatureMuxedUnits,
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ARM::FeatureSlowOddRegister, ARM::FeatureSlowLoadDSubreg,
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ARM::FeatureDontWidenVMOVS, ARM::FeatureExpandMLx,
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ARM::FeatureHasVMLxHazards, ARM::FeatureNEONForFPMovs,
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ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
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ARM::FeatureHasSlowFPVMLx, ARM::FeatureHasSlowFPVFMx,
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ARM::FeatureVMLxForwarding, ARM::FeaturePref32BitThumb,
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ARM::FeatureAvoidPartialCPSR, ARM::FeatureCheapPredicableCPSR,
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ARM::FeatureAvoidMOVsShOp, ARM::FeatureHasRetAddrStack,
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ARM::FeatureHasNoBranchPredictor, ARM::FeatureDSP, ARM::FeatureMP,
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ARM::FeatureVirtualization, ARM::FeatureMClass, ARM::FeatureRClass,
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ARM::FeatureAClass, ARM::FeatureNaClTrap, ARM::FeatureStrictAlign,
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ARM::FeatureLongCalls, ARM::FeatureExecuteOnly, ARM::FeatureReserveR9,
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ARM::FeatureNoMovt, ARM::FeatureNoNegativeImmediates
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};
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const ARMSubtarget *getST() const { return ST; }
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const ARMTargetLowering *getTLI() const { return TLI; }
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public:
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explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const;
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bool enableInterleavedAccessVectorization() { return true; }
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bool shouldFavorBackedgeIndex(const Loop *L) const;
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bool shouldFavorPostInc() const;
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/// Floating-point computation using ARMv8 AArch32 Advanced
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/// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
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/// and Arm MVE are IEEE-754 compliant.
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bool isFPVectorizationPotentiallyUnsafe() {
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return !ST->isTargetDarwin() && !ST->hasMVEFloatOps();
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}
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/// \name Scalar TTI Implementations
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/// @{
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int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty);
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using BaseT::getIntImmCost;
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int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
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int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty, TTI::TargetCostKind CostKind);
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(unsigned ClassID) const {
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bool Vector = (ClassID == 1);
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if (Vector) {
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if (ST->hasNEON())
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return 16;
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if (ST->hasMVEIntegerOps())
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return 8;
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return 0;
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}
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if (ST->isThumb1Only())
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return 8;
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return 13;
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}
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unsigned getRegisterBitWidth(bool Vector) const {
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if (Vector) {
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if (ST->hasNEON())
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return 128;
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if (ST->hasMVEIntegerOps())
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return 128;
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return 0;
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}
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return 32;
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}
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unsigned getMaxInterleaveFactor(unsigned VF) {
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return ST->getMaxInterleaveFactor();
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}
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bool isProfitableLSRChainElement(Instruction *I);
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bool isLegalMaskedLoad(Type *DataTy, Align Alignment);
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bool isLegalMaskedStore(Type *DataTy, Align Alignment) {
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return isLegalMaskedLoad(DataTy, Alignment);
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}
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bool isLegalMaskedGather(Type *Ty, Align Alignment);
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bool isLegalMaskedScatter(Type *Ty, Align Alignment) {
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return isLegalMaskedGather(Ty, Alignment);
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}
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int getMemcpyCost(const Instruction *I);
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int getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, int Index,
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VectorType *SubTp);
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bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
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TTI::ReductionFlags Flags) const;
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bool shouldExpandReduction(const IntrinsicInst *II) const {
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switch (II->getIntrinsicID()) {
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case Intrinsic::experimental_vector_reduce_v2_fadd:
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case Intrinsic::experimental_vector_reduce_v2_fmul:
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// We don't have legalization support for ordered FP reductions.
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if (!II->getFastMathFlags().allowReassoc())
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return true;
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// Can't legalize reductions with soft floats.
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return TLI->useSoftFloat() || !TLI->getSubtarget()->hasFPRegs();
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case Intrinsic::experimental_vector_reduce_fmin:
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case Intrinsic::experimental_vector_reduce_fmax:
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// Can't legalize reductions with soft floats, and NoNan will create
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// fminimum which we do not know how to lower.
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return TLI->useSoftFloat() || !TLI->getSubtarget()->hasFPRegs() ||
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!II->getFastMathFlags().noNaNs();
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default:
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// Don't expand anything else, let legalization deal with it.
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return false;
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}
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}
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int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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int getAddressComputationCost(Type *Val, ScalarEvolution *SE,
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const SCEV *Ptr);
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int getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
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TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
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const Instruction *CxtI = nullptr);
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int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
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unsigned AddressSpace,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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int getInterleavedMemoryOpCost(
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency,
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bool UseMaskForCond = false, bool UseMaskForGaps = false);
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unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
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const Value *Ptr, bool VariableMask,
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Align Alignment, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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bool isLoweredToCall(const Function *F);
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bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
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AssumptionCache &AC,
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TargetLibraryInfo *LibInfo,
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HardwareLoopInfo &HWLoopInfo);
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bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI,
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ScalarEvolution &SE,
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AssumptionCache &AC,
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TargetLibraryInfo *TLI,
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DominatorTree *DT,
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const LoopAccessInfo *LAI);
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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bool emitGetActiveLaneMask() const;
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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bool shouldBuildLookupTablesForConstant(Constant *C) const {
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// In the ROPI and RWPI relocation models we can't have pointers to global
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// variables or functions in constant data, so don't convert switches to
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// lookup tables if any of the values would need relocation.
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if (ST->isROPI() || ST->isRWPI())
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return !C->needsRelocation();
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return true;
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}
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/// @}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
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