mirror of
https://github.com/RPCS3/llvm-mirror.git
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5992856e99
Summary: This patch adds the register + register addressing mode for SVE contiguous load and store intrinsics (LD1 & ST1) Reviewers: sdesmalen, fpetrogalli, efriedma, rengolin Reviewed By: fpetrogalli Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78509
218 lines
8.4 KiB
LLVM
218 lines
8.4 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; LD1B
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;
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define <vscale x 16 x i8> @ld1b_i8(<vscale x 16 x i1> %pg, i8* %a, i64 %index) {
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; CHECK-LABEL: ld1b_i8
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; CHECK: ld1b { z0.b }, p0/z, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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%load = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base)
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ret <vscale x 16 x i8> %load
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}
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define <vscale x 8 x i16> @ld1b_h(<vscale x 8 x i1> %pred, i8* %a, i64 %index) {
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; CHECK-LABEL: ld1b_h:
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; CHECK: ld1b { z0.h }, p0/z, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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%load = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %pred, i8* %base)
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%res = zext <vscale x 8 x i8> %load to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 8 x i16> @ld1sb_h(<vscale x 8 x i1> %pred, i8* %a, i64 %index) {
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; CHECK-LABEL: ld1sb_h:
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; CHECK: ld1sb { z0.h }, p0/z, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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%load = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %pred, i8* %base)
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%res = sext <vscale x 8 x i8> %load to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @ld1b_s(<vscale x 4 x i1> %pred, i8* %a, i64 %index) {
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; CHECK-LABEL: ld1b_s:
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; CHECK: ld1b { z0.s }, p0/z, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %pred, i8* %base)
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%res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @ld1sb_s(<vscale x 4 x i1> %pred, i8* %a, i64 %index) {
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; CHECK-LABEL: ld1sb_s:
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; CHECK: ld1sb { z0.s }, p0/z, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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%load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %pred, i8* %base)
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%res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @ld1b_d(<vscale x 2 x i1> %pred, i8* %a, i64 %index) {
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; CHECK-LABEL: ld1b_d:
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; CHECK: ld1b { z0.d }, p0/z, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %pred, i8* %base)
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%res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @ld1sb_d(<vscale x 2 x i1> %pred, i8* %a, i64 %index) {
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; CHECK-LABEL: ld1sb_d:
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; CHECK: ld1sb { z0.d }, p0/z, [x0, x1]
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; CHECK-NEXT: ret
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%base = getelementptr i8, i8* %a, i64 %index
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%load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %pred, i8* %base)
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%res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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;
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; LD1H
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;
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define <vscale x 8 x i16> @ld1h_i16(<vscale x 8 x i1> %pg, i16* %a, i64 %index) {
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; CHECK-LABEL: ld1h_i16
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; CHECK: ld1h { z0.h }, p0/z, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr i16, i16* %a, i64 %index
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%load = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1> %pg, i16* %base)
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ret <vscale x 8 x i16> %load
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}
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define <vscale x 8 x half> @ld1h_f16(<vscale x 8 x i1> %pg, half* %a, i64 %index) {
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; CHECK-LABEL: ld1h_f16
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; CHECK: ld1h { z0.h }, p0/z, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr half, half* %a, i64 %index
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%load = call <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16(<vscale x 8 x i1> %pg, half* %base)
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ret <vscale x 8 x half> %load
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}
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define <vscale x 4 x i32> @ld1h_s(<vscale x 4 x i1> %pred, i16* %a, i64 %index) {
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; CHECK-LABEL: ld1h_s:
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; CHECK: ld1h { z0.s }, p0/z, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr i16, i16* %a, i64 %index
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%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %pred, i16* %base)
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%res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x i32> @ld1sh_s(<vscale x 4 x i1> %pred, i16* %a, i64 %index) {
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; CHECK-LABEL: ld1sh_s:
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; CHECK: ld1sh { z0.s }, p0/z, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr i16, i16* %a, i64 %index
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%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %pred, i16* %base)
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%res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @ld1h_d(<vscale x 2 x i1> %pred, i16* %a, i64 %index) {
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; CHECK-LABEL: ld1h_d:
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; CHECK: ld1h { z0.d }, p0/z, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr i16, i16* %a, i64 %index
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%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %pred, i16* %base)
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%res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @ld1sh_d(<vscale x 2 x i1> %pred, i16* %a, i64 %index) {
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; CHECK-LABEL: ld1sh_d:
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; CHECK: ld1sh { z0.d }, p0/z, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%base = getelementptr i16, i16* %a, i64 %index
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%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %pred, i16* %base)
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%res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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;
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; LD1W
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;
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define<vscale x 4 x i32> @ld1w(<vscale x 4 x i1> %pg, i32* %a, i64 %index) {
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; CHECK-LABEL: ld1w
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; CHECK: ld1w { z0.s }, p0/z, [x0, x1, lsl #2]
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; CHECK-NEXT: ret
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%base = getelementptr i32, i32* %a, i64 %index
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%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %pg, i32* %base)
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ret <vscale x 4 x i32> %load
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}
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define<vscale x 4 x float> @ld1w_f32(<vscale x 4 x i1> %pg, float* %a, i64 %index) {
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; CHECK-LABEL: ld1w_f32
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; CHECK: ld1w { z0.s }, p0/z, [x0, x1, lsl #2]
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; CHECK-NEXT: ret
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%base = getelementptr float, float* %a, i64 %index
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%load = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32(<vscale x 4 x i1> %pg, float* %base)
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ret <vscale x 4 x float> %load
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}
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define <vscale x 2 x i64> @ld1w_d(<vscale x 2 x i1> %pred, i32* %a, i64 %index) {
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; CHECK-LABEL: ld1w_d:
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; CHECK: ld1w { z0.d }, p0/z, [x0, x1, lsl #2]
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; CHECK-NEXT: ret
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%base = getelementptr i32, i32* %a, i64 %index
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%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %pred, i32* %base)
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%res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x i64> @ld1sw_d(<vscale x 2 x i1> %pred, i32* %a, i64 %index) {
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; CHECK-LABEL: ld1sw_d:
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; CHECK: ld1sw { z0.d }, p0/z, [x0, x1, lsl #2]
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; CHECK-NEXT: ret
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%base = getelementptr i32, i32* %a, i64 %index
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%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %pred, i32* %base)
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%res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %res
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}
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;
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; LD1D
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;
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define <vscale x 2 x i64> @ld1d(<vscale x 2 x i1> %pg, i64* %a, i64 %index) {
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; CHECK-LABEL: ld1d
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; CHECK: ld1d { z0.d }, p0/z, [x0, x1, lsl #3]
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; CHECK-NEXT: ret
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%base = getelementptr i64, i64* %a, i64 %index
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%load = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64(<vscale x 2 x i1> %pg, i64* %base)
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ret <vscale x 2 x i64> %load
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}
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define <vscale x 2 x double> @ld1d_f64(<vscale x 2 x i1> %pg, double* %a, i64 %index) {
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; CHECK-LABEL: ld1d_f64
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; CHECK: ld1d { z0.d }, p0/z, [x0, x1, lsl #3]
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; CHECK-NEXT: ret
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%base = getelementptr double, double* %a, i64 %index
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%load = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1> %pg, double* %base)
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ret <vscale x 2 x double> %load
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1>, i8*)
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declare <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1>, i8*)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1>, i16*)
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declare <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16(<vscale x 8 x i1>, half*)
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declare <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1>, i8*)
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declare <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1>, i16*)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1>, i32*)
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declare <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32(<vscale x 4 x i1>, float*)
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declare <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1>, i8*)
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declare <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1>, i16*)
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declare <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1>, i32*)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64(<vscale x 2 x i1>, i64*)
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declare <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1>, double*)
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