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4d25f3947a
Until we have a real need for computing known bits for scalable vectors I have simply changed the code to bail out for now and pretend we know nothing. I've also fixed up some simple callers of computeKnownBits too. Differential Revision: https://reviews.llvm.org/D80437
88 lines
3.0 KiB
LLVM
88 lines
3.0 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+f64mm -asm-verbose=0 < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; WARN-NOT: warning
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;
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; LD1ROB
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;
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define <vscale x 16 x i8> @ld1rob_i8(<vscale x 16 x i1> %pred, i8* %addr) nounwind {
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; CHECK-LABEL: ld1rob_i8:
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; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pred, i8* %addr)
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ret <vscale x 16 x i8> %res
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}
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;
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; LD1ROH
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;
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define <vscale x 8 x i16> @ld1roh_i16(<vscale x 8 x i1> %pred, i16* %addr) nounwind {
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; CHECK-LABEL: ld1roh_i16:
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; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pred, i16* %addr)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 8 x half> @ld1roh_half(<vscale x 8 x i1> %pred, half* %addr) nounwind {
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; CHECK-LABEL: ld1roh_half:
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; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1> %pred, half* %addr)
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ret <vscale x 8 x half> %res
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}
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;
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; LD1ROW
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;
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define <vscale x 4 x i32> @ld1row_i32(<vscale x 4 x i1> %pred, i32* %addr) nounwind {
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; CHECK-LABEL: ld1row_i32:
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; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pred, i32* %addr)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x float> @ld1row_float(<vscale x 4 x i1> %pred, float* %addr) nounwind {
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; CHECK-LABEL: ld1row_float:
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; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1> %pred, float* %addr)
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ret <vscale x 4 x float> %res
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}
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;
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; LD1ROD
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;
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define <vscale x 2 x i64> @ld1rod_i64(<vscale x 2 x i1> %pred, i64* %addr) nounwind {
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; CHECK-LABEL: ld1rod_i64:
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; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pred, i64* %addr)
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x double> @ld1rod_double(<vscale x 2 x i1> %pred, double* %addr) nounwind {
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; CHECK-LABEL: ld1rod_double:
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; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1> %pred, double* %addr)
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ret <vscale x 2 x double> %res
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1>, i8*)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1>, i16*)
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declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1>, half*)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1>, i32*)
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declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1>, float*)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1>, i64*)
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declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1>, double*)
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