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547 lines
19 KiB
C++
547 lines
19 KiB
C++
//===---------- AArch64CollectLOH.cpp - AArch64 collect LOH pass --*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that collect the Linker Optimization Hint (LOH).
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// This pass should be run at the very end of the compilation flow, just before
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// assembly printer.
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// To be useful for the linker, the LOH must be printed into the assembly file.
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//
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// A LOH describes a sequence of instructions that may be optimized by the
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// linker.
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// This same sequence cannot be optimized by the compiler because some of
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// the information will be known at link time.
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// For instance, consider the following sequence:
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// L1: adrp xA, sym@PAGE
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// L2: add xB, xA, sym@PAGEOFF
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// L3: ldr xC, [xB, #imm]
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// This sequence can be turned into:
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// A literal load if sym@PAGE + sym@PAGEOFF + #imm - address(L3) is < 1MB:
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// L3: ldr xC, sym+#imm
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// It may also be turned into either the following more efficient
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// code sequences:
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// - If sym@PAGEOFF + #imm fits the encoding space of L3.
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// L1: adrp xA, sym@PAGE
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// L3: ldr xC, [xB, sym@PAGEOFF + #imm]
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// - If sym@PAGE + sym@PAGEOFF - address(L1) < 1MB:
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// L1: adr xA, sym
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// L3: ldr xC, [xB, #imm]
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//
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// To be valid a LOH must meet all the requirements needed by all the related
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// possible linker transformations.
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// For instance, using the running example, the constraints to emit
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// ".loh AdrpAddLdr" are:
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// - L1, L2, and L3 instructions are of the expected type, i.e.,
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// respectively ADRP, ADD (immediate), and LD.
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// - The result of L1 is used only by L2.
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// - The register argument (xA) used in the ADD instruction is defined
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// only by L1.
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// - The result of L2 is used only by L3.
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// - The base address (xB) in L3 is defined only L2.
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// - The ADRP in L1 and the ADD in L2 must reference the same symbol using
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// @PAGE/@PAGEOFF with no additional constants
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//
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// Currently supported LOHs are:
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// * So called non-ADRP-related:
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// - .loh AdrpAddLdr L1, L2, L3:
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// L1: adrp xA, sym@PAGE
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// L2: add xB, xA, sym@PAGEOFF
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// L3: ldr xC, [xB, #imm]
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// - .loh AdrpLdrGotLdr L1, L2, L3:
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// L1: adrp xA, sym@GOTPAGE
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// L2: ldr xB, [xA, sym@GOTPAGEOFF]
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// L3: ldr xC, [xB, #imm]
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// - .loh AdrpLdr L1, L3:
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// L1: adrp xA, sym@PAGE
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// L3: ldr xC, [xA, sym@PAGEOFF]
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// - .loh AdrpAddStr L1, L2, L3:
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// L1: adrp xA, sym@PAGE
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// L2: add xB, xA, sym@PAGEOFF
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// L3: str xC, [xB, #imm]
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// - .loh AdrpLdrGotStr L1, L2, L3:
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// L1: adrp xA, sym@GOTPAGE
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// L2: ldr xB, [xA, sym@GOTPAGEOFF]
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// L3: str xC, [xB, #imm]
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// - .loh AdrpAdd L1, L2:
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// L1: adrp xA, sym@PAGE
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// L2: add xB, xA, sym@PAGEOFF
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// For all these LOHs, L1, L2, L3 form a simple chain:
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// L1 result is used only by L2 and L2 result by L3.
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// L3 LOH-related argument is defined only by L2 and L2 LOH-related argument
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// by L1.
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// All these LOHs aim at using more efficient load/store patterns by folding
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// some instructions used to compute the address directly into the load/store.
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//
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// * So called ADRP-related:
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// - .loh AdrpAdrp L2, L1:
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// L2: ADRP xA, sym1@PAGE
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// L1: ADRP xA, sym2@PAGE
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// L2 dominates L1 and xA is not redifined between L2 and L1
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// This LOH aims at getting rid of redundant ADRP instructions.
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//
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// The overall design for emitting the LOHs is:
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// 1. AArch64CollectLOH (this pass) records the LOHs in the AArch64FunctionInfo.
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// 2. AArch64AsmPrinter reads the LOHs from AArch64FunctionInfo and it:
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// 1. Associates them a label.
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// 2. Emits them in a MCStreamer (EmitLOHDirective).
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// - The MCMachOStreamer records them into the MCAssembler.
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// - The MCAsmStreamer prints them.
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// - Other MCStreamers ignore them.
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// 3. Closes the MCStreamer:
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// - The MachObjectWriter gets them from the MCAssembler and writes
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// them in the object file.
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// - Other ObjectWriters ignore them.
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/MapVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-collect-loh"
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STATISTIC(NumADRPSimpleCandidate,
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"Number of simplifiable ADRP dominate by another");
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STATISTIC(NumADDToSTR, "Number of simplifiable STR reachable by ADD");
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STATISTIC(NumLDRToSTR, "Number of simplifiable STR reachable by LDR");
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STATISTIC(NumADDToLDR, "Number of simplifiable LDR reachable by ADD");
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STATISTIC(NumLDRToLDR, "Number of simplifiable LDR reachable by LDR");
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STATISTIC(NumADRPToLDR, "Number of simplifiable LDR reachable by ADRP");
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STATISTIC(NumADRSimpleCandidate, "Number of simplifiable ADRP + ADD");
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#define AARCH64_COLLECT_LOH_NAME "AArch64 Collect Linker Optimization Hint (LOH)"
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namespace {
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struct AArch64CollectLOH : public MachineFunctionPass {
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static char ID;
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AArch64CollectLOH() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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StringRef getPassName() const override { return AARCH64_COLLECT_LOH_NAME; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.setPreservesAll();
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}
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};
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char AArch64CollectLOH::ID = 0;
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} // end anonymous namespace.
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INITIALIZE_PASS(AArch64CollectLOH, "aarch64-collect-loh",
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AARCH64_COLLECT_LOH_NAME, false, false)
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static bool canAddBePartOfLOH(const MachineInstr &MI) {
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// Check immediate to see if the immediate is an address.
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switch (MI.getOperand(2).getType()) {
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default:
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return false;
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case MachineOperand::MO_GlobalAddress:
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case MachineOperand::MO_JumpTableIndex:
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case MachineOperand::MO_ConstantPoolIndex:
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case MachineOperand::MO_BlockAddress:
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return true;
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}
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}
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/// Answer the following question: Can Def be one of the definition
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/// involved in a part of a LOH?
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static bool canDefBePartOfLOH(const MachineInstr &MI) {
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// Accept ADRP, ADDLow and LOADGot.
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switch (MI.getOpcode()) {
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default:
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return false;
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case AArch64::ADRP:
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return true;
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case AArch64::ADDXri:
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return canAddBePartOfLOH(MI);
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case AArch64::LDRXui:
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// Check immediate to see if the immediate is an address.
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switch (MI.getOperand(2).getType()) {
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default:
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return false;
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case MachineOperand::MO_GlobalAddress:
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return MI.getOperand(2).getTargetFlags() & AArch64II::MO_GOT;
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}
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}
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}
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/// Check whether the given instruction can the end of a LOH chain involving a
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/// store.
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static bool isCandidateStore(const MachineInstr &MI, const MachineOperand &MO) {
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switch (MI.getOpcode()) {
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default:
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return false;
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case AArch64::STRBBui:
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case AArch64::STRHHui:
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case AArch64::STRBui:
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case AArch64::STRHui:
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case AArch64::STRWui:
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case AArch64::STRXui:
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case AArch64::STRSui:
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case AArch64::STRDui:
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case AArch64::STRQui:
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// We can only optimize the index operand.
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// In case we have str xA, [xA, #imm], this is two different uses
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// of xA and we cannot fold, otherwise the xA stored may be wrong,
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// even if #imm == 0.
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return MI.getOperandNo(&MO) == 1 &&
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MI.getOperand(0).getReg() != MI.getOperand(1).getReg();
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}
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}
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/// Check whether the given instruction can be the end of a LOH chain
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/// involving a load.
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static bool isCandidateLoad(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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default:
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return false;
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case AArch64::LDRSBWui:
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case AArch64::LDRSBXui:
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case AArch64::LDRSHWui:
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case AArch64::LDRSHXui:
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case AArch64::LDRSWui:
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case AArch64::LDRBui:
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case AArch64::LDRHui:
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case AArch64::LDRWui:
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case AArch64::LDRXui:
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case AArch64::LDRSui:
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case AArch64::LDRDui:
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case AArch64::LDRQui:
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return !(MI.getOperand(2).getTargetFlags() & AArch64II::MO_GOT);
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}
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}
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/// Check whether the given instruction can load a litteral.
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static bool supportLoadFromLiteral(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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default:
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return false;
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case AArch64::LDRSWui:
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case AArch64::LDRWui:
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case AArch64::LDRXui:
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case AArch64::LDRSui:
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case AArch64::LDRDui:
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case AArch64::LDRQui:
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return true;
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}
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}
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/// Number of GPR registers traked by mapRegToGPRIndex()
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static const unsigned N_GPR_REGS = 31;
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/// Map register number to index from 0-30.
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static int mapRegToGPRIndex(MCPhysReg Reg) {
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static_assert(AArch64::X28 - AArch64::X0 + 3 == N_GPR_REGS, "Number of GPRs");
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static_assert(AArch64::W30 - AArch64::W0 + 1 == N_GPR_REGS, "Number of GPRs");
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if (AArch64::X0 <= Reg && Reg <= AArch64::X28)
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return Reg - AArch64::X0;
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if (AArch64::W0 <= Reg && Reg <= AArch64::W30)
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return Reg - AArch64::W0;
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// TableGen gives "FP" and "LR" an index not adjacent to X28 so we have to
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// handle them as special cases.
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if (Reg == AArch64::FP)
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return 29;
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if (Reg == AArch64::LR)
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return 30;
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return -1;
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}
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/// State tracked per register.
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/// The main algorithm walks backwards over a basic block maintaining this
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/// datastructure for each tracked general purpose register.
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struct LOHInfo {
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MCLOHType Type : 8; ///< "Best" type of LOH possible.
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bool IsCandidate : 1; ///< Possible LOH candidate.
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bool OneUser : 1; ///< Found exactly one user (yet).
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bool MultiUsers : 1; ///< Found multiple users.
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const MachineInstr *MI0; ///< First instruction involved in the LOH.
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const MachineInstr *MI1; ///< Second instruction involved in the LOH
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/// (if any).
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const MachineInstr *LastADRP; ///< Last ADRP in same register.
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};
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/// Update state \p Info given \p MI uses the tracked register.
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static void handleUse(const MachineInstr &MI, const MachineOperand &MO,
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LOHInfo &Info) {
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// We have multiple uses if we already found one before.
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if (Info.MultiUsers || Info.OneUser) {
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Info.IsCandidate = false;
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Info.MultiUsers = true;
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return;
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}
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Info.OneUser = true;
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// Start new LOHInfo if applicable.
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if (isCandidateLoad(MI)) {
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Info.Type = MCLOH_AdrpLdr;
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Info.IsCandidate = true;
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Info.MI0 = &MI;
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// Note that even this is AdrpLdr now, we can switch to a Ldr variant
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// later.
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} else if (isCandidateStore(MI, MO)) {
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Info.Type = MCLOH_AdrpAddStr;
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Info.IsCandidate = true;
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Info.MI0 = &MI;
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Info.MI1 = nullptr;
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} else if (MI.getOpcode() == AArch64::ADDXri) {
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Info.Type = MCLOH_AdrpAdd;
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Info.IsCandidate = true;
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Info.MI0 = &MI;
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} else if (MI.getOpcode() == AArch64::LDRXui &&
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MI.getOperand(2).getTargetFlags() & AArch64II::MO_GOT) {
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Info.Type = MCLOH_AdrpLdrGot;
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Info.IsCandidate = true;
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Info.MI0 = &MI;
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}
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}
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/// Update state \p Info given the tracked register is clobbered.
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static void handleClobber(LOHInfo &Info) {
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Info.IsCandidate = false;
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Info.OneUser = false;
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Info.MultiUsers = false;
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Info.LastADRP = nullptr;
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}
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/// Update state \p Info given that \p MI is possibly the middle instruction
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/// of an LOH involving 3 instructions.
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static bool handleMiddleInst(const MachineInstr &MI, LOHInfo &DefInfo,
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LOHInfo &OpInfo) {
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if (!DefInfo.IsCandidate || (&DefInfo != &OpInfo && OpInfo.OneUser))
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return false;
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// Copy LOHInfo for dest register to LOHInfo for source register.
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if (&DefInfo != &OpInfo) {
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OpInfo = DefInfo;
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// Invalidate \p DefInfo because we track it in \p OpInfo now.
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handleClobber(DefInfo);
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} else
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DefInfo.LastADRP = nullptr;
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// Advance state machine.
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assert(OpInfo.IsCandidate && "Expect valid state");
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if (MI.getOpcode() == AArch64::ADDXri && canAddBePartOfLOH(MI)) {
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if (OpInfo.Type == MCLOH_AdrpLdr) {
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OpInfo.Type = MCLOH_AdrpAddLdr;
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OpInfo.IsCandidate = true;
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OpInfo.MI1 = &MI;
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return true;
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} else if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) {
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OpInfo.Type = MCLOH_AdrpAddStr;
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OpInfo.IsCandidate = true;
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OpInfo.MI1 = &MI;
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return true;
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}
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} else {
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assert(MI.getOpcode() == AArch64::LDRXui && "Expect LDRXui");
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assert((MI.getOperand(2).getTargetFlags() & AArch64II::MO_GOT) &&
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"Expected GOT relocation");
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if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) {
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OpInfo.Type = MCLOH_AdrpLdrGotStr;
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OpInfo.IsCandidate = true;
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OpInfo.MI1 = &MI;
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return true;
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} else if (OpInfo.Type == MCLOH_AdrpLdr) {
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OpInfo.Type = MCLOH_AdrpLdrGotLdr;
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OpInfo.IsCandidate = true;
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OpInfo.MI1 = &MI;
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return true;
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}
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}
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return false;
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}
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/// Update state when seeing and ADRP instruction.
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static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI,
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LOHInfo &Info) {
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if (Info.LastADRP != nullptr) {
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LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAdrp:\n"
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<< '\t' << MI << '\t' << *Info.LastADRP);
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AFI.addLOHDirective(MCLOH_AdrpAdrp, {&MI, Info.LastADRP});
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++NumADRPSimpleCandidate;
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}
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// Produce LOH directive if possible.
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if (Info.IsCandidate) {
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switch (Info.Type) {
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case MCLOH_AdrpAdd:
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LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAdd:\n"
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<< '\t' << MI << '\t' << *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpAdd, {&MI, Info.MI0});
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++NumADRSimpleCandidate;
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break;
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case MCLOH_AdrpLdr:
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if (supportLoadFromLiteral(*Info.MI0)) {
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LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdr:\n"
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<< '\t' << MI << '\t' << *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpLdr, {&MI, Info.MI0});
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++NumADRPToLDR;
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}
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break;
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case MCLOH_AdrpAddLdr:
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LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n"
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<< '\t' << MI << '\t' << *Info.MI1 << '\t'
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<< *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpAddLdr, {&MI, Info.MI1, Info.MI0});
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++NumADDToLDR;
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break;
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case MCLOH_AdrpAddStr:
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if (Info.MI1 != nullptr) {
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LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n"
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<< '\t' << MI << '\t' << *Info.MI1 << '\t'
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<< *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpAddStr, {&MI, Info.MI1, Info.MI0});
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++NumADDToSTR;
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}
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break;
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case MCLOH_AdrpLdrGotLdr:
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LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotLdr:\n"
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<< '\t' << MI << '\t' << *Info.MI1 << '\t'
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<< *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpLdrGotLdr, {&MI, Info.MI1, Info.MI0});
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++NumLDRToLDR;
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break;
|
|
case MCLOH_AdrpLdrGotStr:
|
|
LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotStr:\n"
|
|
<< '\t' << MI << '\t' << *Info.MI1 << '\t'
|
|
<< *Info.MI0);
|
|
AFI.addLOHDirective(MCLOH_AdrpLdrGotStr, {&MI, Info.MI1, Info.MI0});
|
|
++NumLDRToSTR;
|
|
break;
|
|
case MCLOH_AdrpLdrGot:
|
|
LLVM_DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGot:\n"
|
|
<< '\t' << MI << '\t' << *Info.MI0);
|
|
AFI.addLOHDirective(MCLOH_AdrpLdrGot, {&MI, Info.MI0});
|
|
break;
|
|
case MCLOH_AdrpAdrp:
|
|
llvm_unreachable("MCLOH_AdrpAdrp not used in state machine");
|
|
}
|
|
}
|
|
|
|
handleClobber(Info);
|
|
Info.LastADRP = &MI;
|
|
}
|
|
|
|
static void handleRegMaskClobber(const uint32_t *RegMask, MCPhysReg Reg,
|
|
LOHInfo *LOHInfos) {
|
|
if (!MachineOperand::clobbersPhysReg(RegMask, Reg))
|
|
return;
|
|
int Idx = mapRegToGPRIndex(Reg);
|
|
if (Idx >= 0)
|
|
handleClobber(LOHInfos[Idx]);
|
|
}
|
|
|
|
static void handleNormalInst(const MachineInstr &MI, LOHInfo *LOHInfos) {
|
|
// Handle defs and regmasks.
|
|
for (const MachineOperand &MO : MI.operands()) {
|
|
if (MO.isRegMask()) {
|
|
const uint32_t *RegMask = MO.getRegMask();
|
|
for (MCPhysReg Reg : AArch64::GPR32RegClass)
|
|
handleRegMaskClobber(RegMask, Reg, LOHInfos);
|
|
for (MCPhysReg Reg : AArch64::GPR64RegClass)
|
|
handleRegMaskClobber(RegMask, Reg, LOHInfos);
|
|
continue;
|
|
}
|
|
if (!MO.isReg() || !MO.isDef())
|
|
continue;
|
|
int Idx = mapRegToGPRIndex(MO.getReg());
|
|
if (Idx < 0)
|
|
continue;
|
|
handleClobber(LOHInfos[Idx]);
|
|
}
|
|
// Handle uses.
|
|
for (const MachineOperand &MO : MI.uses()) {
|
|
if (!MO.isReg() || !MO.readsReg())
|
|
continue;
|
|
int Idx = mapRegToGPRIndex(MO.getReg());
|
|
if (Idx < 0)
|
|
continue;
|
|
handleUse(MI, MO, LOHInfos[Idx]);
|
|
}
|
|
}
|
|
|
|
bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) {
|
|
if (skipFunction(MF.getFunction()))
|
|
return false;
|
|
|
|
LLVM_DEBUG(dbgs() << "********** AArch64 Collect LOH **********\n"
|
|
<< "Looking in function " << MF.getName() << '\n');
|
|
|
|
LOHInfo LOHInfos[N_GPR_REGS];
|
|
AArch64FunctionInfo &AFI = *MF.getInfo<AArch64FunctionInfo>();
|
|
for (const MachineBasicBlock &MBB : MF) {
|
|
// Reset register tracking state.
|
|
memset(LOHInfos, 0, sizeof(LOHInfos));
|
|
// Live-out registers are used.
|
|
for (const MachineBasicBlock *Succ : MBB.successors()) {
|
|
for (const auto &LI : Succ->liveins()) {
|
|
int RegIdx = mapRegToGPRIndex(LI.PhysReg);
|
|
if (RegIdx >= 0)
|
|
LOHInfos[RegIdx].OneUser = true;
|
|
}
|
|
}
|
|
|
|
// Walk the basic block backwards and update the per register state machine
|
|
// in the process.
|
|
for (const MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
|
|
unsigned Opcode = MI.getOpcode();
|
|
switch (Opcode) {
|
|
case AArch64::ADDXri:
|
|
case AArch64::LDRXui:
|
|
if (canDefBePartOfLOH(MI)) {
|
|
const MachineOperand &Def = MI.getOperand(0);
|
|
const MachineOperand &Op = MI.getOperand(1);
|
|
assert(Def.isReg() && Def.isDef() && "Expected reg def");
|
|
assert(Op.isReg() && Op.isUse() && "Expected reg use");
|
|
int DefIdx = mapRegToGPRIndex(Def.getReg());
|
|
int OpIdx = mapRegToGPRIndex(Op.getReg());
|
|
if (DefIdx >= 0 && OpIdx >= 0 &&
|
|
handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx]))
|
|
continue;
|
|
}
|
|
break;
|
|
case AArch64::ADRP:
|
|
const MachineOperand &Op0 = MI.getOperand(0);
|
|
int Idx = mapRegToGPRIndex(Op0.getReg());
|
|
if (Idx >= 0) {
|
|
handleADRP(MI, AFI, LOHInfos[Idx]);
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
handleNormalInst(MI, LOHInfos);
|
|
}
|
|
}
|
|
|
|
// Return "no change": The pass only collects information.
|
|
return false;
|
|
}
|
|
|
|
FunctionPass *llvm::createAArch64CollectLOHPass() {
|
|
return new AArch64CollectLOH();
|
|
}
|