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https://github.com/RPCS3/llvm-mirror.git
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ea2b1a8b94
The port originally had special patterns for extload, mapping them to the same instructions as sextload. It seemed neater to have patterns that match "an extension that is allowed to be signed" and "an extension that is allowed to be unsigned". This was originally meant to be a clean-up, but it does improve the handling of promoted integers a little, as shown by args-06.ll. llvm-svn: 190777
77 lines
1.8 KiB
LLVM
77 lines
1.8 KiB
LLVM
; Test the padding of unextended integer stack parameters. These are used
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; to pass structures.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
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; CHECK-LABEL: f1:
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; CHECK: ar %r2, %r3
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; CHECK: ar %r2, %r4
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; CHECK: ar %r2, %r5
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; CHECK: ar %r2, %r6
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; CHECK: lb {{%r[0-5]}}, 167(%r15)
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; CHECK: lb {{%r[0-5]}}, 175(%r15)
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; CHECK: br %r14
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%addb = add i8 %a, %b
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%addc = add i8 %addb, %c
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%addd = add i8 %addc, %d
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%adde = add i8 %addd, %e
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%addf = add i8 %adde, %f
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%addg = add i8 %addf, %g
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ret i8 %addg
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}
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define i16 @f2(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g) {
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; CHECK-LABEL: f2:
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; CHECK: ar %r2, %r3
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; CHECK: ar %r2, %r4
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; CHECK: ar %r2, %r5
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; CHECK: ar %r2, %r6
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; CHECK: ah %r2, 166(%r15)
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; CHECK: ah %r2, 174(%r15)
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; CHECK: br %r14
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%addb = add i16 %a, %b
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%addc = add i16 %addb, %c
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%addd = add i16 %addc, %d
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%adde = add i16 %addd, %e
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%addf = add i16 %adde, %f
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%addg = add i16 %addf, %g
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ret i16 %addg
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}
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define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
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; CHECK-LABEL: f3:
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; CHECK: ar %r2, %r3
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; CHECK: ar %r2, %r4
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; CHECK: ar %r2, %r5
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; CHECK: ar %r2, %r6
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; CHECK: a %r2, 164(%r15)
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; CHECK: a %r2, 172(%r15)
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; CHECK: br %r14
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%addb = add i32 %a, %b
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%addc = add i32 %addb, %c
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%addd = add i32 %addc, %d
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%adde = add i32 %addd, %e
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%addf = add i32 %adde, %f
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%addg = add i32 %addf, %g
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ret i32 %addg
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}
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define i64 @f4(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g) {
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; CHECK-LABEL: f4:
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; CHECK: agr %r2, %r3
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; CHECK: agr %r2, %r4
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; CHECK: agr %r2, %r5
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; CHECK: agr %r2, %r6
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; CHECK: ag %r2, 160(%r15)
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; CHECK: ag %r2, 168(%r15)
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; CHECK: br %r14
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%addb = add i64 %a, %b
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%addc = add i64 %addb, %c
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%addd = add i64 %addc, %d
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%adde = add i64 %addd, %e
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%addf = add i64 %adde, %f
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%addg = add i64 %addf, %g
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ret i64 %addg
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}
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