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d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
109 lines
3.1 KiB
YAML
109 lines
3.1 KiB
YAML
# RUN: llc -mtriple=arm-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
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#
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# This checks alignment of a block when a CPE is placed before/after a
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# block (as e.g. opposed to splitting up a block).
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#
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "arm-arm--eabi"
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declare i32 @llvm.arm.space(i32, i32) #0
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define dso_local i32 @CP() #1 {
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entry:
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%res = alloca half, align 2
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store half 0xH706B, half* %res, align 2
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%0 = load half, half* %res, align 2
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%tobool = fcmp une half %0, 0xH0000
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br i1 %tobool, label %LA, label %END
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LA: ; preds = %entry
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%1 = call i32 @llvm.arm.space(i32 1000, i32 undef)
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br label %END
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END: ; preds = %LA, %entry
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%2 = call i32 @llvm.arm.space(i32 100, i32 undef)
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ret i32 42
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}
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #2
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attributes #0 = { nounwind "target-features"="+v8.2a,+fullfp16" }
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attributes #1 = { "target-features"="+v8.2a,+fullfp16" }
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attributes #2 = { nounwind }
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...
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---
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name: CP
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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liveins:
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 4
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offsetAdjustment: 0
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maxAlignment: 2
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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- { id: 0, name: res, type: default, offset: -2, size: 2, alignment: 2,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -2, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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constants:
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- id: 0
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value: half 0xH706B
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alignment: 2
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isTargetSpecific: false
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#CHECK: bb.{{.*}} (align 2):
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#CHECK: successors:
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#CHECK: CONSTPOOL_ENTRY 1, %const{{.*}}, 2
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# We want this block to be 4 byte aligned:
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#CHECK: bb.{{.*}}.LA (align 4):
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body: |
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.2(0x30000000)
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$sp = frame-setup SUBri $sp, 4, 14, $noreg, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_offset 4
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renamable $s0 = VLDRH %const.0, 0, 14, $noreg :: (load 2 from constant-pool)
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VCMPZH renamable $s0, 14, $noreg, implicit-def $fpscr_nzcv
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VSTRH killed renamable $s0, $sp, 1, 14, $noreg :: (store 2 into %ir.res)
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FMSTAT 14, $noreg, implicit-def $cpsr, implicit killed $fpscr_nzcv
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Bcc %bb.2, 0, killed $cpsr
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bb.1.LA:
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successors: %bb.2(0x80000000)
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dead renamable $r0 = SPACE 1000, undef renamable $r0
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bb.2.END:
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dead renamable $r0 = SPACE 100, undef renamable $r0
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$r0 = MOVi 42, 14, $noreg, $noreg
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$sp = ADDri $sp, 4, 14, $noreg, $noreg
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BX_RET 14, $noreg, implicit killed $r0
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...
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