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684e62e531
Whether an instruction is deemed to have side effects in determined by whether it has a tblgen pattern that emits a single instruction. Because of the way a lot of the the vcvt instructions are specified either in dagtodag code or with patterns that emit multiple instructions, they don't get marked as not having side effects. This just marks them as not having side effects manually. It can help especially with instruction scheduling, to not create artificial barriers, but one of these tests also managed to produce fewer instructions. Differential Revision: https://reviews.llvm.org/D81639
52 lines
1.6 KiB
LLVM
52 lines
1.6 KiB
LLVM
; RUN: llc -o - %s | FileCheck %s
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; Make sure we do not try to compute liveness for FPSCR which in this case
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; is read before being written to (this is fine because becase FPSCR is
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; reserved).
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target triple = "thumbv7s-apple-ios"
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%struct.wibble = type { double }
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@global = common global i32 0, align 4
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@global.1 = common global i32 0, align 4
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; CHECK-LABEL: eggs:
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; CHECK: sub sp, #8
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; VMRS instruction comes before any other instruction writing FPSCR:
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; CHECK-NOT: vcmp
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; CHECK: vmrs {{r[0-9]}}, fpscr
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; CHECK; vcmp
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; ...
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; CHECK: add sp, #8
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; CHECK: bx lr
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define i32 @eggs(double* nocapture readnone %arg) {
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bb:
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%tmp = alloca %struct.wibble, align 4
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%tmp1 = bitcast %struct.wibble* %tmp to i8*
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%tmp2 = tail call i32 @llvm.flt.rounds()
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%tmp3 = ptrtoint %struct.wibble* %tmp to i32
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%tmp4 = sitofp i32 %tmp3 to double
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%tmp5 = fmul double %tmp4, 0x0123456789ABCDEF
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%tmp6 = fptosi double %tmp5 to i32
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%tmp7 = fcmp une double %tmp5, 0.000000e+00
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%tmp8 = sitofp i32 %tmp6 to double
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%tmp9 = fcmp une double %tmp5, %tmp8
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%tmp10 = and i1 %tmp7, %tmp9
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%tmp11 = sext i1 %tmp10 to i32
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%tmp12 = add nsw i32 %tmp11, %tmp6
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store i32 %tmp12, i32* @global, align 4
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%tmp13 = icmp ne i32 %tmp12, 0
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%tmp14 = icmp ne i32 %tmp2, 0
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%tmp15 = and i1 %tmp14, %tmp13
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br i1 %tmp15, label %bb16, label %bb18
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bb16: ; preds = %bb
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%tmp17 = load i32, i32* @global.1, align 4
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br label %bb18
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bb18: ; preds = %bb16, %bb
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ret i32 undef
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}
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declare i32 @llvm.flt.rounds()
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declare i32 @zot(...)
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